In one embodiment, an apparatus includes n electrical communication channels, m optical communication media interfaces, and a plurality of muxes. The plurality of muxes are configured to receive an information stream, the information stream carried over the n electrical communication channels and the m optical communication media interfaces. The plurality of muxes are further configured to transform the information stream from v virtual lanes, each virtual lane comprising a plurality of data blocks from the information stream and an alignment block, wherein v is a positive integer multiple of the least common multiple of m and n.

A plurality of fabric controllers distributed throughout a fabric attached architecture and each associated with at least one resource node. The plurality of fabric controllers configured to control each associated resource node. Resources of the resource nodes are utilized in virtual environments responsive to respective fabric controllers issuing instructions received from the fabric attached architecture to respective resource nodes.

A video data communication system for transmitting ultra-high definition video or three dimensional video stream over a packet switched network, including: an input receiving or obtaining plural high definition video streams representing a part of the ultra-high definition video stream or three dimensional video stream; a packet switched network transmitting at least part of the plural high definition video streams in parallel from a transmitter to a receiver; a receiver receiving the plural high definition video streams after the transmission over a packet switched network; a videogenlocker for generating a clock for the received high definition video streams and for synchronizing the received high definition video streams; and a combiner combining the synchronized received high definition video streams into a received ultra-high definition video stream or three dimensional video stream.

Rapid channel failure detection and recovery in wireless communication networks is needed in order to meet, among other things, carrier class Ethernet channel standards. Thus, resilient wireless packet communications is provided using a physical layer link aggregation protocol with a hardware-assisted rapid channel failure detection algorithm and load balancing, preferably in combination. This functionality may be implemented in a Gigabit Ethernet data access card with an engine configured accordingly. In networks with various topologies, these features may be provided in combination with their existing protocols.

An apparatus is provided that includes communication channels, and m communication media interfaces, and v virtual lanes. V is a positive integer multiple of the least common multiple of m and n. An information stream is transferred into data and alignment blocks striped across all of the v virtual lanes, the blocks being communicated from the virtual lanes onto the communication channels. The blocks are received on the communication channels. Each of the communication channels transmits a different portion of the blocks striped across all of the v virtual lanes. In more particular embodiments, v>=n>=m. The communication media interfaces can be electrical and optical. Each of the communication channels can include a SerDes interface operating at least 5 Gigabits per second. Furthermore, each of the m communication media interfaces is configured to transmit a different stream of information over a single optical fiber.

The PCS and FEC layers are combined into a single layer and the number of lanes is set at four lanes. The combination allows removal of many modules as compared to a serial arrangement of a PCS layer and an FEC layer. The reduction in the number of lanes, as compared to 100 Gbps Ethernet, provides a further simplification or cost reduction by further reducing the needed gates of an ASIC to perform the functions. Changing the lanes in the FEC layer necessitates changing the alignment marker structure. In the preferred embodiment a lane zero marker is used as the first alignment marker in each lane to allow rapid sync. A second alignment marker indicating the particular lane follows the first alignment marker.

Embodiments described herein provide a method for providing a compatible backplane operation mechanism for 2.5-gigabit Ethernet. A first input of data including a first sequence-ordered set in compliance with a first interface protocol is received from a medium access control (MAC) layer. The first input of data is encoded into four outputs of encoded data including a second sequence-ordered set in compliance with a second interface protocol. The first sequence-ordered set in a first form of a sequence code followed by three bytes of data is mapped to the second sequence-ordered set in a second form of consecutive units of the sequence code followed by an encoded data byte. The four parallel outputs of encoded data are serialized into a serial output. The serial output to a linking partner is transmitted on a physical layer of an Ethernet link at a speed specified in the second interface protocol.

A Chip-to-Chip (C2C) interface utilizing Flexible Ethernet (FlexE) includes circuitry configured to provide a packet interface on a single card or over backplane/fabric links between two devices, wherein the circuitry comprises flow control and channelization for the FlexE. Each of the two devices can include any of a Network Processor (NPU), a Fabric Interface Card (FIC), a framer, and a mapper. A rate of the FlexE can be increased to support additional information for the flow control and the channelization.

A signal processing apparatus, signal processing method, program, and signal transmission system can transmit 8K or 4K video signals stably through a device of 100 Gbps. A signal processor includes a mapping unit configured to map an 8K or 4K video signal onto first data streams, prescribed by a predetermined format, of plural channels, and a multiplexer configured to generate plural first data blocks by scrambling the first data streams of either odd-numbered or even-numbered channels, first bits by first bits, invert the polarity of data blocks which are part of the first data blocks, generate plural second data blocks by 8B/10B-converting the first data streams of the other channels, second bits by second bits, and generate serial second data streams of plural lanes by multiplexing the first data blocks and the second data blocks. The processor is applicable to a broadcasting camera, for example.

Rapid channel failure detection and recovery in wireless communication networks is needed in order to meet, among other things, carrier class Ethernet channel standards. Thus, resilient wireless packet communications is provided using a physical layer link aggregation protocol with a hardware-assisted rapid channel failure detection algorithm and load balancing, preferably in combination. This functionality may be implemented in a Gigabit Ethernet data access card with an engine configured accordingly. In networks with various topologies, these features may be provided in combination with their existing protocols.