In some embodiments, an apparatus includes a switch fabric having at least a first switch stage and a second switch stage, an edge device operatively coupled to the switch fabric and a management module. The edge device is configured to send a first portion of a data stream to the switch fabric such that the first portion of the data stream is received at a queue of the second switch stage of the switch fabric via the first switch stage of the switch fabric. The management module is configured to send a flow control signal configured to trigger the edge device to suspend transmission of a second portion of the data stream when a congestion level of the queue of the second switch stage of the switch fabric satisfies a condition in response to the first portion of the data stream being received at the queue.

Switchless interconnect fabric message distribution includes end-to-end partitioning of message pathways or multiple priority levels with interrupt capability. A switchless interconnect fabric message distribution system includes a data distribution module and at least two host-bus adapters connected to the data distribution module. The data distribution module includes partition first in first out buffers. Each of the host-bus adapters includes an input manager connected to input priority first in first out buffers and an output manager connected to priority first in first out buffers.

An external processing system includes a port configured to exchange signals with a router and one or more processors configured to instantiate an operating system and a hypervisor based on information provided by the router in response to the external processing system being connected to the router. The processors implement a user plane layer that generates feedback representative of a processing load and provides the feedback to the router via the port. The router includes a port allocated to an external processing system and a controller that provides the information representing the operating system and hypervisor in response to connection of the external processing system. The controller also receives feedback indicating a processing load at the external processing system. A queue holds packets prior to providing the packets to the external processing system. The controller discards one or more of the packets from the queue based on the feedback.

An external processing system includes a port configured to exchange signals with a router and one or more processors configured to instantiate an operating system and a hypervisor based on information provided by the router in response to the external processing system being connected to the router. The processors implement a user plane layer that generates feedback representative of a processing load and provides the feedback to the router via the port. The router includes a port allocated to an external processing system and a controller that provides the information representing the operating system and hypervisor in response to connection of the external processing system. The controller also receives feedback indicating a processing load at the external processing system. A queue holds packets prior to providing the packets to the external processing system. The controller discards one or more of the packets from the queue based on the feedback.

Disclosed is a method of routing a flow of packets from a source node to a destination node over multiple pathways only when the destination node has determined and advised the source node that a packet reordering resource is available for use with multipath operation. Also disclosed is a method of detecting packet loss without incurring timeout delays when routing packets in a flow of packets over multiple pathways from a source node to a destination node. Further disclosed is a method of dynamically avoiding slower paths when routing packets between a source node and a destination node along multiple pathways. Also disclosed is a method of avoiding overflow of a destination node reorder window when routing packets between a source node and a destination node along multiple pathways.

Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements performs flow based computations on wavelets of data. Each processing element has a compute element and a routing element. Each compute element has memory. Each router enables communication via wavelets with nearest neighbors in a 2D mesh. A compute element receives a wavelet. If a control specifier of the wavelet is a first value, then instructions are read from the memory of the compute element in accordance with an index specifier of the wavelet. If the control specifier is a second value, then instructions are read from the memory of the compute element in accordance with a virtual channel specifier of the wavelet. Then the compute element initiates execution of the instructions.

Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements performs flow based computations on wavelets of data. Each processing element has a compute element and a routing element. Each compute element has memory. Each router enables communication via wavelets with nearest neighbors in a 2D mesh. A compute element receives a wavelet. If a control specifier of the wavelet is a first value, then instructions are read from the memory of the compute element in accordance with an index specifier of the wavelet. If the control specifier is a second value, then instructions are read from the memory of the compute element in accordance with a virtual channel specifier of the wavelet. Then the compute element initiates execution of the instructions.

Examples describe a manner of scheduling packet segment fetches at a rate that is based on one or more of: a packet drop indication, packet drop rate, incast level, operation of queues in SAF or VCT mode, or fabric congestion level. Headers of packets can be fetched faster than payload or body portions of packets and processed prior to queueing of all body portions. In the event a header is identified as droppable, fetching of the associated body portions can be halted and any body portion that is queued can be discarded. Fetch overspeed can be applied for packet headers or body portions associated with packet headers that are approved for egress.

Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements performs flow-based computations on wavelets of data. Each processing element has a respective compute element and a respective routing element. Instructions executed by the compute element include operand specifiers, some specifying a data structure register storing a data structure descriptor describing an operand as a fabric vector or a memory vector. The data structure descriptor further describes various attributes of the fabric vector: length, microthreading eligibility, number of data elements to receive, transmit, and/or process in parallel, virtual channel and task identification information, whether to terminate upon receiving a control wavelet, and whether to mark an outgoing wavelet a control wavelet.

There is provided methods and apparatuses for transferring photonic cells or frames between a photonic switch and an electronic switch enabling a scalable data center cloud system with photonic functions transparently embedded into an electronic chassis. In various embodiments, photonic interface functions may be transparently embedded into existing switch chips (or switch cards) without changes in the line cards. The embedded photonic interface functions may provide the switch cards with the ability to interface with both existing line cards and photonic switches. In order to embed photonic interface functions without changes on the existing line cards, embodiments use two-tier buffering with a pause signalling or pause messaging scheme for managing the two-tier buffer memories.