H04L49/508

Packet forwarding method and apparatus
10298495 · 2019-05-21 · ·

Embodiments of the present invention disclose a packet forwarding method and apparatus. The method includes: receiving, by a first scheduler, a target packet; sending the target packet to a destination physical egress port corresponding to the egress port information, and increasing, according to the queue identifier, a queue length of a virtual queue corresponding to the queue identifier by the packet length; sending update information to a second scheduler, where the update information includes that the queue length of the virtual queue is increased by the packet length; and decreasing the queue length of the virtual queue by the packet length according to a bandwidth scheduling result that is corresponding to the update information and sent by the second scheduler. In this way, even if back pressure appears in the destination physical egress port corresponding to the target packet, that the first scheduler sends the target packet is not affected.

OVERLOAD PROTECTION ENGINE
20180331960 · 2018-11-15 ·

A fabric interface, including: an ingress port to receive incoming network traffic; a host interface to forward the incoming network traffic to a host; and a virtualization-aware overload protection engine including: an overload detector to detect an overload condition on the incoming network traffic; a packet inspector to inspect packets of the incoming network traffic; and a prioritizer to identify low priority packets to be dropped, and high priority packets to be forwarded to the host.

END TO END FLOW CONTROL
20180316616 · 2018-11-01 ·

A network device implementing the subject system for end to end flow control may include at least one processor circuit that may be configured to detect that congestion is being experienced by at least one queue of a port and identify another network device that is transmitting downstream traffic being queued at the at least one queue of the port that is at least partially causing the congestion. The at least one processor circuit may be further configured to generate an end to end flow control message that comprises an identifier of the port, the end to end flow control message indicating that the downstream traffic should be flow controlled at the another network device. The at least one processor circuit may be further configured to transmit, out-of-band and through at least one intermediary network device, the end to end flow control message to the another network device.

End to end flow control

A network device implementing the subject system for end to end flow control may include at least one processor circuit that may be configured to detect that congestion is being experienced by at least one queue of a port and identify another network device that is transmitting downstream traffic being queued at the at least one queue of the port that is at least partially causing the congestion. The at least one processor circuit may be further configured to generate an end to end flow control message that comprises an identifier of the port, the end to end flow control message indicating that the downstream traffic should be flow controlled at the another network device. The at least one processor circuit may be further configured to transmit, out-of-band and through at least one intermediary network device, the end to end flow control message to the another network device.

NETWORK DATA PROCESSOR HAVING PER-INPUT PORT VIRTUAL OUTPUT QUEUES
20180198736 · 2018-07-12 ·

Various embodiments of a virtual output queue system within a network element enables per-input port virtual output queues within a network data processor of the network element. In one embodiment, each port managed by a network data processor has an associated set of virtual output queues for each output port on the network data element. In one embodiment, network data processor hardware supports per-processor VOQs and per-input port VOQs are enabled in hardware for layer 3 forwarding by overloading layer 2 forwarding logic. In such embodiment, a mapping table is generated to enable virtual per-input port VOQs for layer 3 forwarding logic using layer 2 logic that is otherwise unused during layer 3 forwarding. In one embodiment, multiple traffic classes can be managed per-input port when using per-input port VOQs. In one embodiment, equal cost multi-path (ECMP) and link aggregation support is also enabled.

Network data processor having per-input port virtual output queues

Various embodiments of a virtual output queue system within a network element enables per-input port virtual output queues within a network data processor of the network element. In one embodiment, each port managed by a network data processor has an associated set of virtual output queues for each output port on the network data element. In one embodiment, network data processor hardware supports per-processor VOQs and per-input port VOQs are enabled in hardware for layer 3 forwarding by overloading layer 2 forwarding logic. In such embodiment, a mapping table is generated to enable virtual per-input port VOQs for layer 3 forwarding logic using layer 2 logic that is otherwise unused during layer 3 forwarding. In one embodiment, multiple traffic classes can be managed per-input port when using per-input port VOQs. In one embodiment, equal cost multi-path (ECMP) and link aggregation support is also enabled.

NETWORK DATA PROCESSOR HAVING PER-INPUT PORT VIRTUAL OUTPUT QUEUES
20170005951 · 2017-01-05 ·

Various embodiments of a virtual output queue system within a network element enables per-input port virtual output queues within a network data processor of the network element. In one embodiment, each port managed by a network data processor has an associated set of virtual output queues for each output port on the network data element. In one embodiment, network data processor hardware supports per-processor VOQs and per-input port VOQs are enabled in hardware for layer 3 forwarding by overloading layer 2 forwarding logic. In such embodiment, a mapping table is generated to enable virtual per-input port VOQs for layer 3 forwarding logic using layer 2 logic that is otherwise unused during layer 3 forwarding. In one embodiment, multiple traffic classes can be managed per-input port when using per-input port VOQs. In one embodiment, equal cost multi-path (ECMP) and link aggregation support is also enabled.

Apparatus, system, and method of out-of-order delivery of wireless communication frames

For example, a wireless communication station (STA) may be configured to determine whether a stream of frames is suitable for out-of-order delivery from a first Medium Access Control layer (MAC-layer) process to a second MAC-layer process, the second MAC-layer process is above the first MAC-layer process; and, based on a determination that the stream of frames is suitable for out-of-order delivery, to deliver to the second MAC-layer process one or more frames of the stream of frames according to an out-of-order delivery scheme.

HARDWARE ACCELERATION TECHNIQUES USING FLOW SELECTION
20250337687 · 2025-10-30 ·

In some embodiments, a method receives a packet for a flow associated with a workload. Based on an indicator for the flow, the method determines whether the flow corresponds to one of an elephant flow or a mice flow. Only when the flow is determined to correspond to an elephant flow, the method enables a hardware acceleration operation on the packet. The hardware acceleration operation may include hardware operation offload, receive side scaling, and workload migration.

METHOD AND SYSTEM FOR SOLVING BYPASS-BASED MODULAR MULTI-CHIPLET DEADLOCK
20250330432 · 2025-10-23 ·

A method and system for solving bypass-based modular multi-chiplet deadlock include polling each border router by means of time slice round-robin scheduling inside each chiplet; when processing upon arrival of the time slice of the border router, the border router is polled based on the internal time slice of the chiplet in a switchover manner to trigger the bypass mechanism of choke packets, and an output port is reserved between the border router and the destination router by using a look-ahead signal to build a bypass, and reserving a network interface and a rollback mechanism when the bypass packet pops up. The present disclosure aims at achieving deadlock-free in realizing bypass-based modular multi-chiplet design requirements in a multi-chiplet architecture under 2.5D packaging.