Patent classifications
H04L49/9052
Wide elastic buffer
A receiving device uses an elastic buffer that is wider than the number of data elements transferred in each cycle. To compensate for frequency differences between the transmitter and the receiver, the transmitting device periodically sends a skip request with a default number of skip data elements. If the elastic buffer is filling, the receiving device ignores one or more of the skip data elements. If the elastic buffer is emptying, the receiving device adds one or more skip data elements to the skip request. To maintain the ordering of data despite the manipulation of the skip data elements, two rows of the wide elastic buffer are read at a time. This allows construction of a one-row result from any combination of the data elements of the two rows. The column pointers are adjusted appropriately, to ensure that they continue to point to the next data to be read.
SERVICE BASED INTELLIGENT PACKET-IN BUFFERING MECHANISM FOR OPENFLOW SWITCHES BY HAVING VARIABLE BUFFER TIMEOUTS
A method is performed by a network device acting as a switch in a Software Defined Networking (SDN) network, where the switch is coupled to a controller in the SDN network. The method implements variable buffer timeout output actions. The method includes generating a flow entry that includes a packet matching criteria and an output action that specifies a buffer timeout value, receiving a packet for forwarding, determining whether the packet matches the packet matching criteria of the flow entry, and storing the packet in a buffer of the switch in response to determining that the packet matches the packet matching criteria of the flow entry, the buffer to temporarily store the packet while the controller determines processing for the packet. The method further includes associating the buffered packet with the buffer timeout value specified in the flow entry and transmitting a portion of the packet to the controller.
Memory buffer management method and system having multiple receive ring buffers
The present invention is directed to a method and system of memory management that features dual buffer rings, each of which includes descriptors identifying addresses of a memory space, referred to as buffers, in which portions of data packets are stored. Typically, the header segment of each data packet is stored at a first set of a plurality of buffers, and the portion of the payload segment that does not fit among the buffers of the first set is stored in the buffers of a second set. In this manner, the size of the individual buffers associated with the first buffer rings may be kept to the smallest size of useable storage space, and the buffers corresponding to the second buffer ring may be arbitrary in size.
Efficient Means of Combining Network Traffic for 64Bit and 31Bit Workloads
A method, system and computer-usable medium are disclosed for performing a network traffic combination operation. With the network traffic combination operation, a plurality of input queues are defined by an operating system for an adapter based upon workload type (e.g., as determined by a transport layer). Additionally, the operating system defines each input queue to match a virtual memory architecture of the transport layer (e.g., one input queue is defined as 31 bit and other input queue is defined as 64 bit). When data is received off the wire as inbound data from a physical NIC, the network adapter associates the inbound data with the appropriate memory type. Thus, data copies are eliminated and memory consumption and associated storage management operations are reduced for the smaller bit architecture communications while allowing the operating system to continue executing in a larger bit architecture configuration.
Efficient Means of Combining Network Traffic for 64Bit and 31Bit Workloads
A method, system and computer-usable medium are disclosed for performing a network traffic combination operation. With the network traffic combination operation, a plurality of input queues are defined by an operating system for an adapter based upon workload type (e.g., as determined by a transport layer). Additionally, the operating system defines each input queue to match a virtual memory architecture of the transport layer (e.g., one input queue is defined as 31 bit and other input queue is defined as 64 bit). When data is received off the wire as inbound data from a physical NIC, the network adapter associates the inbound data with the appropriate memory type. Thus, data copies are eliminated and memory consumption and associated storage management operations are reduced for the smaller bit architecture communications while allowing the operating system to continue executing in a larger bit architecture configuration,
Hierarchical Packet Buffer System
A switching device includes a primary memory and an traffic manager. The primary memory buffers packets for temporary storage. The traffic manager monitors consumed resources in the device related to the buffering of packets in the primary memory. The traffic manager migrates packets buffered in the primary memory to a secondary memory when the consumed resources exceed a certain threshold. The traffic manager also controls dequeuing of the packets from the primary memory and the secondary memory.
SYSTEMS AND METHODS FOR SCALABLE NETWORK BUFFER MANAGEMENT
The disclosed computer-implemented method for scalable network buffer management may include (1) receiving, via a connection to a client, data to be transmitted to a cloud service, (2) buffering the data in at least one data buffer, (3) determining that the data will not be transmitted to the cloud service within a timeout period for the client connection, (4) delaying reception of additional data from the client connection for a portion of the timeout period, and (5) before the timeout period has elapsed, buffering data from the client connection in at least one secondary data buffer, wherein the secondary data buffer is smaller in size than the data buffer. Various other methods, systems, and computer-readable media are also disclosed.
Wide Elastic Buffer
A receiving device uses an elastic buffer that is wider than the number of data elements transferred in each cycle. To compensate for frequency differences between the transmitter and the receiver, the transmitting device periodically sends a skip request with a default number of skip data elements. If the elastic buffer is filling, the receiving device ignores one or more of the skip data elements. If the elastic buffer is emptying, the receiving device adds one or more skip data elements to the skip request. To maintain the ordering of data despite the manipulation of the skip data elements, two rows of the wide elastic buffer are read at a time. This allows construction of a one-row result from any combination of the data elements of the two rows. The column pointers are adjusted appropriately, to ensure that they continue to point to the next data to be read.
Methods and apparatus for memory allocation and reallocation in networking stack infrastructures
Methods and apparatus for memory allocation and reallocation in networking stack infrastructures. Unlike prior art monolithic networking stacks, the exemplary networking stack architecture described hereinafter includes various components that span multiple domains (both in-kernel, and non-kernel). For example, unlike traditional socket based communication, disclosed embodiments can transfer data directly between the kernel and user space domains. A user space networking stack is disclosed that enables extensible, cross-platform-capable, user space control of the networking protocol stack functionality. The user space networking stack facilitates tighter integration between the protocol layers (including TLS) and the application or daemon. Exemplary systems can support multiple networking protocol stack instances (including an in-kernel traditional network stack). Due to this disclosed architecture, physical memory allocations (and deallocations) may be more flexibly implemented.
Method and System for Optimizing Buffer Reservation and Utilization
A system for controlling memory buffer reservation comprising a transmitter, a receiver and buffer control logic is provided. The transmitter is configured to transmit a plurality of memory requests on two or more request channels, the plurality of memory requests comprising at least one priority request transmitted on a first request channel. The receiver comprises a plurality of buffers, each buffer having an associated credit, wherein each request channel is provided with a credit value based on the number of buffers allocated to receive memory requests from the corresponding request channel, where at least one credit is provided to the first request channel. The buffer control logic enables the first request channel to use a buffer allocated to a second request channel by utilizing a credit provided to the second request channel for transmitting the priority request to the receiver when a credit provided to first request channel is unavailable.