Patent classifications
H04L49/9068
IN-BAND MANAGEMENT INTERFACE WITH USER SPACE DATAPATH
A method of utilizing the same hardware network interface card (NIC) in a gateway of a datacenter to communicate datacenter tenant packet traffic and packet traffic for a set of applications that execute in the user space of the gateway and utilize a network stack in the kernel space of the gateway. The method sends and receives packets for the datacenter tenant packet traffic through a packet datapath in the user space. The method sends incoming packets from the NIC to the set of applications through the datapath in the user space, a user-kernel transport driver connecting the kernel network stack to the datapath in the user space, and the kernel network stack. The method receives outgoing packets at the NIC from the set of applications through the kernel network stack, the user-kernel transport driver, and the data path in the user space.
NETWORK INTERFACE DEVICE
A network interface device has an interface configured to interface with a network. The interface is configured to at least one of receive data from the network and put data onto the network. The network interface device has an application specific integrated device with a plurality of data processing pipelines to process at least one of data which has been received from the network and data which is to be put onto said network and an FPGA arranged in a path parallel to the data processing pipelines.
Techniques for indicating and changing network communication settings of a computer host
A technique for setting network communications for a computer host having multiple network interface controllers (NICs) includes performing network communication for a baseboard management controller (BMC) using a first NIC. In response to actuation of a switch of a network connector jack that is associated with the first NIC, a switching signal is sent from the switch to the BMC. In response to receipt of the switching signal at the BMC, network communication for the BMC is performed using a second NIC.
Scheduling method for virtual processors based on the affinity of NUMA high-performance network buffer resources
A scheduling method for virtual processors based on the affinity of NUMA high-performance network buffer resources, including: in a NUMA architecture, when a network interface card (NIC) of a virtual machine is started, getting distribution of the buffer of the NIC on each NUMA node; getting affinities of each NUMA node for the buffer of the network interface card on the basis of an affinity relationship between each NUMA node; determining a target NUMA node in combination with the distribution of the buffer of the NIC on each NUMA node and NUMA node affinities for the buffer of the NIC; scheduling the virtual processor to the CPU on the target NUMA node. The problem of affinity between the VCPU of the virtual machine and the buffer of the NIC not being optimal in the NUMA architecture is solved to reduce the speed of VCPU processing network packets.
Fine grain traffic shaping offload for a network interface card
A network interface card with traffic shaping capabilities and methods of network traffic shaping with a network interface card are provided. The network interface card and method can shape traffic originating from one or more applications executing on a host network device. The applications can execute in a virtual machine or containerized computing environment. The network interface card and method can perform or include several traffic shaping mechanisms including, for example and without limitation, a delayed completion mechanism, a time-indexed data structure, a packet builder, and a memory manager.
Systems for building data structures with highly scalable algorithms for a distributed LPM implementation
Described are programmable IO devices configured to perform operations. These operations comprise: determining a set of range-based elements for a network; sorting the set of range-based elements according to a global order among the range-based elements; generating an interval table from the sorted range-based elements; generating an interval binary search tree from the interval table; propagating data stored in subtrees of interior stages of the interval binary search tree to subtrees of a last stage of the interval binary search tree such that the interior stages do not comprise data; converting the interval binary search tree to a Pensando Tree; compressing multiple levels of the Pensando Tree into cache-lines; and assembling the cache-lines in the memory unit such that each stage can compute an address of a next-cache line to be fetched by a next stage.
Logical router with multiple routing components
Some embodiments provide a method for implementing a logical router in a network. The method receives a definition of a logical router for implementation on a set of network elements. The method defines several routing components for the logical router. Each of the defined routing components includes a separate set of routes and separate set of logical interfaces. The method implements the several routing components in the network. In some embodiments, the several routing components include one distributed routing component and several centralized routing components.
A TRANSMITTER THAT DOES NOT RESEND A PACKET DESPITE RECEIPT OF A MESSAGE TO RESEND THE PACKET
A processing device includes an internal transmitter to receive packets and to forward those packets across a link to an external receiver external to the processing device. The internal transmitter is to receive a portion of a packet and to begin transmitting the portion across the link to the external receiver before the entire overall packet, of which the portion is a part, is received and validated. For a packet determined to have an error, the internal transmitter does not resend the overall packet across the link even if a message is received from the external receiver to resend the overall packet.
SENDING PACKETS USING OPTIMIZED PIO WRITE SEQUENCES WITHOUT SFENCES AND OUT OF ORDER CREDIT RETURNS
Methods and apparatus for sending packets using optimized PIO write sequences without sfences and out-of-order credit returns. Sequences of Programmed Input/Output (PIO) write instructions to write packet data to a PIO send memory are received by a processor in an original order and executed out of order, resulting in the packet data being written to send blocks in the PIO send memory out of order, while the packets themselves are stored in sequential order once all of the packet data is written. The packets are egressed out of order by egressing packet data contained in the send blocks to an egress block using a non-sequential packet order that is different than the sequential packet order. In conjunction with egressing the packets, corresponding credits are returned in the non-sequential packet order. A block list comprising a linked list and a free list are used to facilitate out-of-order packet egress and corresponding out-of-order credit returns.
Hybrid tag matching
A method for communication includes posting, by a software process, a set of buffers in a memory of a host processor and creating in the memory a list of labels associated respectively with the buffers. The software process pushes a first part of the list to a network interface controller (NIC), while retaining a second part of the list in the memory under control of the software process. Upon receiving a message containing a label, sent over a network, the NIC compares the label to the labels in the first part of the list and, upon finding a match to the label, writes data conveyed by the message to a buffer in the memory. Upon a failure to find the match in the first part of the list, the NIC passes the message from the NIC to the software process for handling using the second part of the list.