Various systems and methods for implementing time-based flexible packet scheduling are provided herein. A network interface device for implementing time-based flexible packet scheduling including a packet parser to: determine from analyzing a packet, a corresponding processing element that is used to process the packet; and store the packet in a queue; and a coordinator circuit to: determine a timing of when the processing element is active in a computing unit; and modify the priority of the packet in the queue based on the timing of when the processing element is active in the computing unit.

Various systems and methods for implementing a flexible packet processing mechanism are provided herein. A network interface device for implementing flexible packet processing includes a packet parser to: receive a packet; and determine from analyzing the packet, a corresponding processing element that is used to process the packet; and a coordinator circuit to: determine whether the processing element is active in a computing unit; load the processing element when it is not active; and forward the packet to the processing element.

Various systems and methods for implementing flexible packet scheduling are provided herein. A network interface device for implementing flexible packet scheduling includes a packet parser to: receive a packet; determine from analyzing the packet, a corresponding processing element that is used to process the packet; and store the packet in a queue; and a coordinator circuit to: determine whether the processing element is active in a computing unit; and modify the priority of the packet in the queue based on whether the processing element is active in the computing unit.

A device that is configured to generate reports to send to a server comprises at least one processor configured to generate the reports. Upon loss of connection, generated reports are stored in a buffer in memory of the device, capable of storing k reports. The first generated report is stored in a first part of the buffer, a most recently generated report is stored in a second part of the buffer, while the remaining reports are stored in a third part of the buffer. When the third part is full, a sampling algorithm is used to select the k2 reports to store in the third part.

A controller area network has a plurality of nodes in communication through a bus. The nodes have controllers and computer readable instructions that, when executed, perform the steps of: receiving a new message; inserting the new message into the queue in order of priority if the queue is not full; refusing the new message if the queue is full and the priority of the new message is lower than the priorities of current messages in the queue; inserting the new message into the queue in order of priority if the queue is full and the priority of the new message is higher than a priority of at least one of the current messages; removing the new message from the queue if the current time exceeds an expiration indicator; sending the new message to the controller for transmission and holding the new message in the queue during transmission; and removing the new message from the queue after successful transmission.

In one embodiment, the apparatus is configured to perform receiving, at the apparatus, a plurality of packets of information to be transmitted from the apparatus to a node, generating at least one queue of the plurality of packets of information to be transported to the node, and discarding at least one packet from the queue at a specific time and/or based on a timing characteristic of the at least one packet to be discarded.

A packet communication apparatus is configured to relay packets transmitted and received between information processing apparatuses. The packet communication apparatus includes: a network interface connectable to a network; a CPU to be a destination of at least one of a plurality of packets to be received through the network interface; a first buffer configured to hold the packets destined to the CPU in order to output the packets to the CPU; a second buffer having a plurality of planes and configured to hold copies of the packets destined to the CPU held in the first buffer in one of the plurality of planes; and a reception history controller configured to store a copy of a packet to a specified plane of the second buffer or to save copies of packets held in the second buffer to another storage area based on usage of the first buffer.

A controller area network has a plurality of nodes in communication through a bus. The nodes have controllers and computer readable instructions that, when executed, perform the steps of: receiving a new message; inserting the new message into the queue in order of priority if the queue is not full; refusing the new message if the queue is full and the priority of the new message is lower than the priorities of current messages in the queue; inserting the new message into the queue in order of priority if the queue is full and the priority of the new message is higher than a priority of at least one of the current messages; removing the new message from the queue if the current time exceeds an expiration indicator; sending the new message to the controller for transmission and holding the new message in the queue during transmission; and removing the new message from the queue after successful transmission.

An information processing apparatus that communicates with a device includes a control unit that performs control to store, in a first operation mode, predetermined communication information that is information used for communication with the device in a first memory, and store, in a second operation mode different from the first operation mode, the predetermined communication information in a second memory whose capacity is smaller than a capacity of the first memory. When shifting from the first operation mode to the second operation mode, the control unit performs control of changing a setting of the predetermined communication information such that a size of a saving destination of packet data transferred to the second memory is a predetermined size.