A data processing apparatus includes a first memory control unit and a second memory control unit. The first memory control unit performs data transfer via an interface of a first bus form. The second memory control unit performs data transfer between a memory device connected via an interface of a second bus form. The first memory control unit and the second memory control unit are connected by a local bus. The memory control unit is provided in the local bus to control, via a predetermined buffer, a write access or a read access to the first memory control unit from the second memory control unit and control, via the predetermined buffer, a read access or a write access to the second memory control unit from the first memory control unit.