Disclosed is a method and apparatus for encoding/decoding a video. According to an embodiment, provided is a method of setting a level for each of one or more regions, including decoding a definition syntax element related to level definition and a designation syntax element related to target designation from a bitstream; defining one or more levels based on the definition syntax element; and setting a target level designated by the designation syntax element among the defined levels for a target region designated by the designation syntax element.

A video processing apparatus implemented in a chip includes an on-chip prediction buffer and a processing circuit. The on-chip prediction buffer is shared by a plurality of coding tools for prediction, and is used to store reference data. The processing circuit supports the coding tools for prediction, reads a plurality of first reference data from the on-chip prediction buffer as input data of a first coding tool that is included in the coding tools and enabled by the processing circuit, and writes output data of the first coding tool enabled by the processing circuit into the on-chip prediction buffer as a plurality of second reference data.

A video processing apparatus implemented in a chip includes an on-chip prediction buffer and a processing circuit. The on-chip prediction buffer is shared by a plurality of coding tools for prediction, and is used to store reference data. The processing circuit supports the coding tools for prediction, reads a plurality of first reference data from the on-chip prediction buffer as input data of a first coding tool that is included in the coding tools and enabled by the processing circuit, and writes output data of the first coding tool enabled by the processing circuit into the on-chip prediction buffer as a plurality of second reference data.

A device includes an encoder, decoder, codec or combination thereof and inline hardware conversion units that are operative to convert stored image data into one of: an HDR/WCG format and an SDR/SCG format during the conversion process. Each of the inline hardware conversion units is operative to perform the conversion process independent of another read operation with the memory that stores the image data to be converted. In one example, an encoding unit is operative to perform a write operation with a memory to store the converted image data after completing the conversion process. In another example, a decoding unit is operative to perform a read operation with the memory to retrieve the image data from the memory before initiating the conversion process. In another example, an encoder/decoder unit is operative to perform at least one of: the read operation and the write operation.

A device includes an encoder, decoder, codec or combination thereof and inline hardware conversion units that are operative to convert stored image data into one of: an HDR/WCG format and an SDR/SCG format during the conversion process. Each of the inline hardware conversion units is operative to perform the conversion process independent of another read operation with the memory that stores the image data to be converted. In one example, an encoding unit is operative to perform a write operation with a memory to store the converted image data after completing the conversion process. In another example, a decoding unit is operative to perform a read operation with the memory to retrieve the image data from the memory before initiating the conversion process. In another example, an encoder/decoder unit is operative to perform at least one of: the read operation and the write operation.

In some embodiments, an apparatus includes a memory configured to store data and a controller coupled to the memory. The controller is configured to receive, from a computing device coupled to the apparatus, one or more frames of a digital video. The controller is also configured to analyze one or more components of the memory. The controller is further configured to determine a set of states for the one or more components of the memory based on the analysis of the one or more components of the memory. The controller is further configured to determine a first encoding rate for the digital video from a plurality of encoding rates based on the set of states for the one or more components of the memory. The controller is further configured to encode the digital video based on the first encoding rate and to store the encoded digital video in the memory.

A video encoder for encoding a video into a data stream using motion compensated prediction for inter predicted blocks, comprising a hypothesis number control, configured to control a number of prediction hypotheses of the inter predicted blocks within a predetermined portion of the video to meet a predetermined criterion.

Examples described herein relate to decoding and encoding signals. A method of performing signal decoding operations on one or more portions of a signal is presented. The performing is based at least in part on information embedded in one or more values received in one or more encoded data layers transmitted within a stream of encoded data, wherein said values are associated with transformed coefficients intended to be processed by a decoder for deriving elements of the signal, and wherein said information comprises an indication of watermarking information associated with the signal.

Examples described herein relate to decoding and encoding signals. A method of performing signal decoding operations on one or more portions of a signal is presented. The performing is based at least in part on information embedded in one or more values received in one or more encoded data layers transmitted within a stream of encoded data, wherein said values are associated with transformed coefficients intended to be processed by a decoder for deriving elements of the signal, and wherein said information comprises an indication of watermarking information associated with the signal.

A display driver circuit configured to drive a display panel includes a memory, a decoder, and a controller. The memory stores first data using data from outside of the display driver circuit. The decoder decodes the stored first data. The controller generates compression data using the decoded first data. While an image based on the decoded first data is displayed on the display panel, when second data based on the data from the outside are not stored in the memory after the first data are stored in the memory, the controller controls the decoder such that the decoder does not operate and controls the memory such that the compression data are stored in the memory.