H04N19/433

Techniques for memory bandwidth optimization in bi-predicted motion vector refinement
11595681 · 2023-02-28 · ·

A method and apparatus for encoding of a video sequence in an encoder or decoding of the video sequence in a decoder includes parsing an initial motion vector from the video sequence associated with a block. A plurality of samples are determined and pre-fetched to permit both motion vector refinement and motion compensation based on parsing the initial motion vector. Motion vector refinement is performed to determine a final motion vector using a first subset of the plurality of samples, and motion compensation is performed using a second subset of the plurality of samples.

Reference sample memory size restrictions for intra block copy
11509919 · 2022-11-22 · ·

A method for video decoding at a decoder is provided. In the method, reconstructed samples of a reconstructed block of a picture are stored in a first reference sample memory. The first reference sample memory is configured to store at least one set of a number of luma samples and corresponding chroma samples of the reconstructed block. Further, reconstructed samples of a current block of the picture are stored in a second reference sample memory. The second reference sample memory is configured to store only one set of the number of luma samples and corresponding chroma samples of the current block. A current sub-block in the current block is reconstructed using an intra block copy (IBC) mode based on the stored reconstructed samples of a reference sub-block of the reconstructed block or the stored reconstructed samples of a reference sub-block of the current block.

ENCODER, DECODER, ENCODING METHOD, AND DECODING METHOD
20220368929 · 2022-11-17 ·

An encoder includes circuitry and memory coupled to the circuitry. Given id indicating a lower temporal sublayer other than a highest temporal sublayer in temporal sublayers, the circuitry calculates a DPB output time [id] for a picture in the lower temporal sublayer. In doing so, the circuitry of the encoder subtracts a DPB output delta [id] provided for each of the temporal sublayers from a DPB output delay shared between the temporal sublayers, and given maxid indicating the highest temporal sublayer, calculates the DPB output delta [id] by subtracting a CPB removal delay [maxid] and an offset [id] from a CPB removal delay [id]. Next, the circuitry stores the offset [id] in a bitstream.

System and method for temporal differencing with variable complexity

A system and method for transmitting compressed video. A transmitter receives uncompressed video data from a video source, and compresses it using one or more reference frames. A receiver receives the compressed video data and decodes it, using the same reference frames, to form display data. The reference frames are stored in compressed form in both the transmitter and the receiver. Each frame of display data becomes a reference frame for the decoding of a subsequent frame.

System and method for temporal differencing with variable complexity

A system and method for transmitting compressed video. A transmitter receives uncompressed video data from a video source, and compresses it using one or more reference frames. A receiver receives the compressed video data and decodes it, using the same reference frames, to form display data. The reference frames are stored in compressed form in both the transmitter and the receiver. Each frame of display data becomes a reference frame for the decoding of a subsequent frame.

SUPPORTING MULTIPLE PARTITION SIZES USING A UNIFIED PIXEL INPUT DATA INTERFACE FOR FETCHING REFERENCE PIXELS IN VIDEO ENCODERS

A system for storing and providing video pixel data for video encoding is disclosed. The system comprises a memory storage and a cache storage. The system further comprises a controller. The controller is configured to receive a request that causes transferring of a reference pixel block of a video, wherein the video is being encoded using the reference pixel block. The controller is configured to determine whether the reference pixel block has at least a portion that is outside a frame of the video. In response to the determination of the reference pixel block having at least a portion outside the frame of the video, the controller is configured to cause a portion of the reference pixel block of the video inside the frame of the video to be fetched from a memory storage and stored in a cache storage, pad a remaining missing portion of the reference pixel block of the video outside the frame of the video with padding pixel data to form the reference pixel block, and transfer the reference pixel block in response to the request.

MULTI-HYPOTHESIS PREDICTION

A video encoder for encoding a video into a data stream using motion compensated prediction for inter predicted blocks, comprising a hypothesis number control, configured to control a number of prediction hypotheses of the inter predicted blocks within a predetermined portion of the video to meet a predetermined criterion.

Display driver circuit supporting operation in a low power mode of a display device

A display driver circuit configured to drive a display panel includes a memory, a decoder, and a controller. The memory stores first data using data from outside of the display driver circuit. The decoder decodes the stored first data. The controller generates compression data using the decoded first data. While an image based on the decoded first data is displayed on the display panel, when second data based on the data from the outside are not stored in the memory after the first data are stored in the memory, the controller controls the decoder such that the decoder does not operate and controls the memory such that the compression data are stored in the memory.

VIDEO DECODING APPARATUS AND METHOD
20230040891 · 2023-02-09 · ·

According to an example embodiment, a video decoding apparatus may be provided. The video decoding apparatus may include a central processing unit (CPU) configured to parse first header data included in an input bit-stream and generate a first register set based on the parsed first header data; and a decoder configured to decode the input bit-stream based on input parameters obtained through the first register set, wherein CPU is configured to parse second header data included in a second bit-stream of the input bit-stream of a second frame subsequent to the first frame while the decoder decodes a first bit-stream corresponding to the first frame.

SIGNALING NON-SCALABLE-NESTED HYPOTHETICAL REFERENCE VIDEO DECODER INFORMATION
20230100097 · 2023-03-30 ·

Examples of video encoding methods and apparatus and video decoding methods and apparatus are described. An example method of video processing includes performing a conversion between a video and a bitstream of the video, wherein the bitstream includes one or more output layer sets comprising one or more video layers according to a format rule, wherein the format rule specifies that a non-scalable-nested supplemental enhancement information, SEI, message that includes information regarding hypothetical reference decoder, HRD, is applicable to all output layer sets that include same video layers as the bitstream.