H04N19/433

Video processing in a data storage device

A method and apparatus for video processing on a data storage device. A chip bound architecture includes a CMOS coupled to one or more NAND die, the CMOS including one or more processors, memories, and error correction code (ECC) engines capable of processing video data. According to certain embodiments, macroblocks are correlated between two I-frames, including motion vectors to define different locations of correlated macroblocks. A P-frame may be determined from a previous I-frame and its correlated macroblocks and motion vectors, while a B-frame may be determined from two or more adjacent I-frames with concomitant macroblocks and motion vectors, as well as P-frames associated with an adjacent I-frame.

Hierarchical packing of syntax elements

A method operates within an integrated circuit having a plurality of processing lanes. For each of a first and second processing lanes, the method determines a number of packed data words among one or more packed data words associated with the respective processing lane, associates the number of packed data words with a used field of the processing lane, wherein the used field indicates the number of packed data words in the processing lane; and stores the one or more packed data words in a variable record length memory based, at least in part, on the used field of the processing lane.

Hierarchical packing of syntax elements

A method operates within an integrated circuit having a plurality of processing lanes. For each of a first and second processing lanes, the method determines a number of packed data words among one or more packed data words associated with the respective processing lane, associates the number of packed data words with a used field of the processing lane, wherein the used field indicates the number of packed data words in the processing lane; and stores the one or more packed data words in a variable record length memory based, at least in part, on the used field of the processing lane.

IMAGE ENCODER, AN IMAGE SENSING DEVICE, AND AN OPERATING METHOD OF THE IMAGE ENCODER
20230164292 · 2023-05-25 ·

The present disclosure provides an image encoder. The image encoder is configured to encode an original image and reduce compression loss. The image encoder comprises an image signal processor and a compressor. The image signal processor is configured to receive a first frame image and a second frame image and generates a compressed image of the second frame image using a boundary pixel image of the first frame image. The image signal processor may include memory configured to store first reference pixel data which is the first frame image. The compressor is configured to receive the first reference pixel data from the memory and generate a bitstream obtained by encoding the second frame image based on a difference value between the first reference pixel data and the second frame image. The image signal processor generates a compressed image of the second frame image using the bitstream generated by the compressor.

MOTION VECTOR OBTAINING METHOD AND APPARATUS

This application provides a motion vector obtaining method and apparatus. The method includes: determining a target offset vector of a block and identifier information of a target picture, wherein the block comprises at least one sub-block; determining a location of the sub-block; determining, as a target location coordinate value of a collocated sub-block, a location coordinate value obtained by performing a clipping operation on an initial location coordinate value in a range, wherein the initial location coordinate value is based on the location of the sub-block and the target offset vector; and obtaining a motion vector of the sub-block based on a motion vector corresponding to the target location coordinate value. Thus, a range of the target offset vector is limited, so that a quantity of memory read times can be reduced in a process of obtaining the motion vector of the collocated sub-block.

Method and apparatus for video coding
11627328 · 2023-04-11 · ·

Aspects of the disclosure provide methods and apparatuses for video encoding/decoding. In some examples, an apparatus for video decoding includes processing circuitry. The processing circuitry determines an area with sample values available in a reference sample memory for use in a reconstruction of a current block. Further, the processing circuitry updates a history based list for storing locations of previously reconstructed samples of a single value string mode. The locations are limited within the area. Then, the processing circuitry reconstructs, based on the history based list, a string of the single value string mode within the current block.

PICTURE TIMING INFORMATION SIGNALING IN CODED VIDEO
20230105511 · 2023-04-06 ·

Examples of video encoding methods and apparatus and video decoding methods and apparatus are described. An example method of video processing includes performing a conversion between a video and a bitstream of the video comprising one or more output layer sets according to a rule, wherein the rule specifies that a supplemental enhancement information (SEI) network abstraction layer (NAL) unit that includes a scalable-nested SEI message carrying picture timing information is not included due to use of a same picture timing in all output layer sets in the bitstream.

SIMPLIFICATION OF COMBINED INTER-INTRA PREDICTION
20230106340 · 2023-04-06 ·

Techniques for implementing video processing techniques are described. In one example implementation, a method of video processing includes determining, for a conversion between a current block of a video coded using a combined inter and intra prediction (CIIP) coding technique and a bitstream representation of the video, an intra-prediction mode of the current block independently from an intra-prediction mode of a neighboring block. The CIIP coding technique uses an intermedia inter prediction value and an intermedia intra prediction value to derive a final prediction value of the current block. The method also includes performing the conversion based on the determining.

Multi-hypothesis prediction

A video encoder for encoding a video into a data stream using motion compensated prediction for inter predicted blocks, comprising a hypothesis number control, configured to control a number of prediction hypotheses of the inter predicted blocks within a predetermined portion of the video to meet a predetermined criterion.

EFFICIENT DECODING AND RENDERING OF INTER-CODED BLOCKS IN A GRAPHICS PIPELINE

Innovations in video decoding and rendering operations for inter-coded blocks in a graphics pipeline, in which at least some of the operations are performed using a graphics processing unit (“GPU”), are described. For example, a video playback tool receives encoded data for a current picture and performs operations to decode the encoded data and reconstruct the current picture. For a given inter-coded block of the current picture, a graphics primitive represents texture values as a point for processing by the GPU. The graphics primitive can have one or more attributes, including a motion vector, a block size, a display index value (indicating a location in a display buffer), and/or a residual index value (indicating a location of residual values). The operations performed by the video playback tool can include interpolation of sample values at fractional-sample offsets and motion compensation performed for inter-coded blocks in multiple passes for different block sizes.