H04N19/433

Virtual memory access bandwidth verification (VMBV) in video coding
09762899 · 2017-09-12 · ·

A method is provided that includes determining a target picture virtual memory access (VMA) bandwidth rate, wherein the target picture VMA bandwidth rate indicates a maximum VMA bandwidth rate for motion compensation of a picture, and verifying the target picture VMA bandwidth rate for a compressed video bit stream.

Virtual memory access bandwidth verification (VMBV) in video coding
09762899 · 2017-09-12 · ·

A method is provided that includes determining a target picture virtual memory access (VMA) bandwidth rate, wherein the target picture VMA bandwidth rate indicates a maximum VMA bandwidth rate for motion compensation of a picture, and verifying the target picture VMA bandwidth rate for a compressed video bit stream.

Chroma cache architecture in block processing pipelines

Methods and apparatus for caching reference data in a block processing pipeline. A cache may be implemented to which reference data corresponding to motion vectors for blocks being processed in the pipeline may be prefetched from memory. Prefetches for the motion vectors may be initiated one or more stages prior to a processing stage. Cache tags for the cache may be defined by the motion vectors. When a motion vector is received, the tags can be checked to determine if there are cache block(s) corresponding to the vector (cache hits) in the cache. Upon a cache miss, a cache block in the cache is selected according to a replacement policy, the respective tag is updated, and a prefetch (e.g., via DMA) for the respective reference data is issued.

Chroma cache architecture in block processing pipelines

Methods and apparatus for caching reference data in a block processing pipeline. A cache may be implemented to which reference data corresponding to motion vectors for blocks being processed in the pipeline may be prefetched from memory. Prefetches for the motion vectors may be initiated one or more stages prior to a processing stage. Cache tags for the cache may be defined by the motion vectors. When a motion vector is received, the tags can be checked to determine if there are cache block(s) corresponding to the vector (cache hits) in the cache. Upon a cache miss, a cache block in the cache is selected according to a replacement policy, the respective tag is updated, and a prefetch (e.g., via DMA) for the respective reference data is issued.

Mixed NAL Unit Type Picture Constraints
20210409780 · 2021-12-30 ·

A video coding mechanism is disclosed. The mechanism includes receiving a bitstream comprising a flag and a plurality of sub-pictures associated with a picture. The plurality of sub-pictures are contained in a plurality of video coding layer (VCL) network abstraction layer (NAL) units. The mechanism determines that VCL NAL units of one or more of the sub-pictures of the picture all have a first particular value of NAL unit type and other VCL NAL units in the picture all have a different second particular value of NAL unit type based on a value of the flag. One or more of the sub-pictures are decoded based on the first particular value of NAL unit type and the second particular value of NAL unit type. One or more of the sub-pictures are forwarded for display as part of a decoded video sequence.

METHOD AND APPARATUS FOR POINT CLOUD CODING
20220232253 · 2022-07-21 · ·

In some examples, an apparatus for point cloud compression/decompression includes processing circuitry. The processing circuitry determines a flag that indicates an enable/disable control for saving coding state in a largest coding unit (LCU) based coding of a point cloud. In some examples, the processing circuitry stores coding state information before a coding of a first LCU; and in response to the flag indicating an enable control, the processing circuitry restores, a coding state according to the stored coding state information before a coding of a second LCU. In some examples, in response to the flag indicating an enable control, the processing circuitry stores the coding state information before the coding of the first LCU. In some examples, in response to the flag indicating a disable control, the processing circuitry skip the storing/restoring of the coding state information.

Encoder, decoder, encoding method, and decoding method

An encoder includes: circuitry; and memory coupled to the circuitry. In operation, the circuitry: derives a base motion vector to be used in predicting a current block to be encoded; derives a first motion vector different from the base motion vector; derives a motion vector difference based on a difference between the base motion vector and the first motion vector; determines whether the motion vector difference is greater than a threshold; modifies the first motion vector when the motion vector difference is determined to be greater than the threshold, and does not modify the first motion vector when the motion vector difference is determined not to be greater than the threshold; and encodes the current block using the first motion vector modified or the first motion vector not modified.

Encoder, decoder, encoding method, and decoding method

An encoder includes: circuitry; and memory coupled to the circuitry. In operation, the circuitry: derives a base motion vector to be used in predicting a current block to be encoded; derives a first motion vector different from the base motion vector; derives a motion vector difference based on a difference between the base motion vector and the first motion vector; determines whether the motion vector difference is greater than a threshold; modifies the first motion vector when the motion vector difference is determined to be greater than the threshold, and does not modify the first motion vector when the motion vector difference is determined not to be greater than the threshold; and encodes the current block using the first motion vector modified or the first motion vector not modified.

ENCODER, A DECODER AND CORRESPONDING METHODS USING IBC SEARCH RANGE OPTIMIZATION FOR ARBITRARY CTU SIZE
20210400304 · 2021-12-23 ·

The present disclosure provides a method of video coding implemented by a decoding device or an encoding device for optimum usage of a hardware reference memory buffer, wherein a group of reference coding tree units (CTUs) for Intra Block Copy (IBC) mode prediction of a current block of a current CTU is determined based on a size of the current CTU, and wherein the reference samples of the current block are obtained from the group of reference CTUs.

Method and apparatus for encoding or decoding video data in FRUC mode with reduced memory accesses

The present disclosure concerns a method and a device for encoding or decoding video data. It concerns more particularly the encoding according to a particular encoding mode using a decoder side motion vector derivation mode referenced as frame-rate up conversion mode or FRUC mode. It concerns encoding and decoding improvement which reduce the need for memory accesses when using an encoding mode where the motion information is predicted using a decoder side motion vector derivation method.