There is provided in one embodiment an apparatus having an image sensor array. In one embodiment, the image sensor array can include monochrome pixels and color sensitive pixels. The monochrome pixels can be pixels without wavelength selective color filter elements. The color sensitive pixels can include wavelength selective color filter elements.

An imaging device that can obtain imaging data corresponding to high-resolution images in a short period of time is provided. The imaging device includes a pixel including a photoelectric conversion element and n (n is an integer more than 2 inclusive) retention circuits. The photoelectric conversion element and the n retention circuits are stacked. One electrode of the photoelectric conversion element is electrically connected to the first to n-th retention circuits. The retention circuits include OS transistors with an extremely low off-state current feature, and can retain imaging data for a long time. In the first to n-th periods, the imaging device obtains the first to n-th imaging data and retains it in the first to n-th retention circuits. Then, the first to n-th imaging data retained in the first to n-th retention circuits are read out. The read imaging data is output outside the imaging data through AD conversion.

An imaging system includes a pixel array configured to generate image charge voltage signals in response to incident light received from an external scene. An infrared illumination source is deactivated during the capture of a first image of the external scene and activated during the capture of a second image of the external scene. An array of sample and hold circuits is coupled to the pixel array. Each sample and hold circuit is coupled to a respective pixel of the pixel array and includes first and second capacitors to store first and second image charge voltage signals of the captured first and second images, respectively. A column voltage domain differential amplifier is coupled to the first and second capacitors to determine a difference between the first and second image charge voltage signals to identify an object in a foreground of the external scene.

There is provided in one embodiment an apparatus having an image sensor array. In one embodiment, the image sensor array can include monochrome pixels and color sensitive pixels. The monochrome pixels can be pixels without wavelength selective color filter elements. The color sensitive pixels can include wavelength selective color filter elements.

There is provided in one embodiment an apparatus having an image sensor array. In one embodiment, the image sensor array can include monochrome pixels and color sensitive pixels. The monochrome pixels can be pixels without wavelength selective color filter elements. The color sensitive pixels can include wavelength selective color filter elements.

A global shutter readout circuit includes a reset transistor coupled between a reset voltage and a bitline. A pixel enable transistor is coupled between the reset transistor and a source follower transistor. First and second terminals of the pixel enable transistor are coupled together in response to a pixel enable signal coupled to a third terminal of the pixel enable transistor. A first storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor. A first storage capacitor is coupled to the first storage transistor. A second storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor. A second storage capacitor is coupled to the second storage transistor. A row select transistor is coupled to the source follower transistor to generate an output signal from the global shutter readout circuit.

A global shutter readout circuit includes a reset transistor coupled between a reset voltage and a bitline. A pixel enable transistor is coupled between the reset transistor and a source follower transistor. First and second terminals of the pixel enable transistor are coupled together in response to a pixel enable signal coupled to a third terminal of the pixel enable transistor. A first storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor. A first storage capacitor is coupled to the first storage transistor. A second storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor. A second storage capacitor is coupled to the second storage transistor. A row select transistor is coupled to the source follower transistor to generate an output signal from the global shutter readout circuit.

There is provided in one embodiment an apparatus having an image sensor array. In one embodiment, the image sensor array can include monochrome pixels and color sensitive pixels. The monochrome pixels can be pixels without wavelength selective color filter elements. The color sensitive pixels can include wavelength selective color filter elements.

An imaging device includes a photoelectric conversion layer, a counter electrode, a first electrode, a second electrode, a first transfer gate, a second transfer gate, a first amplification transistor, and a second amplification transistor. The first transistor outputs a signal corresponding to the potential of the first gate in a first readout period in which the first transfer gate suppresses transfer of signal charges. The first readout period includes a first period in which the second transfer gate allows transfer of signal charges. The second transistor outputs a signal corresponding to the potential of the second gate in a second readout period in which the second transfer gate suppresses transfer of signal charges. The second readout period includes a second period in which the first transfer gate allows transfer of signal charges.

An imaging device includes a photoelectric conversion layer, a counter electrode, a first electrode, a second electrode, a first transfer gate, a second transfer gate, a first amplification transistor, and a second amplification transistor. The first transistor outputs a signal corresponding to the potential of the first gate in a first readout period in which the first transfer gate suppresses transfer of signal charges. The first readout period includes a first period in which the second transfer gate allows transfer of signal charges. The second transistor outputs a signal corresponding to the potential of the second gate in a second readout period in which the second transfer gate suppresses transfer of signal charges. The second readout period includes a second period in which the first transfer gate allows transfer of signal charges.