Patent classifications
H04N25/627
ANTI-ECLIPSE CIRCUITRY WITH TRACKING OF FLOATING DIFFUSION RESET LEVEL
Imagers and associated devices and systems are disclosed herein. In one embodiment, an imager includes a pixel array and control circuitry operably coupled to the pixel array. The pixel array includes an imaging pixel configured to produce a reset signal and a non-imaging pixel configured to produce a nominal reset signal. The control circuitry is configured to produce an output signal based at least in part on one of (a) the nominal reset signal when distortion at the imaging pixel exceeds a threshold and (b) the reset signal when distortion does not exceed the threshold.
SOLID-STATE IMAGING DEVICE AND CONTROL METHOD OF THE SAME
The present invention is a solid-state imaging device including: a pixel array section including a plurality of unit pixels capable of accumulating charge photoelectrically converted by a photoelectric conversion section in a predetermined floating diffusion (FD) region; a system control section that controls the pixel array section; and a pixel signal reading mechanism that reads a pixel signal based on the charge from the predetermined FD region of a unit pixel of the plurality of unit pixels under control of the system control section. The pixel signal reading mechanism may include an AD converter that performs AD conversion processing on the pixel signal read, and a determination section that performs brightness/darkness determination of light received by the unit pixel on the basis of the pixel signal read in a determination phase. The determination section selectively controls execution or stop of the AD conversion processing by the AD converter on a pixel signal to be subsequently read according to a result of the determination.
DRIVER CHIP
A driver chip is provided. The driver chip includes a light-emitting module and a wafer substrate. The light-emitting module has multiple pins. The wafer substrate has a first surface and a second surface. The wafer substrate includes a photodiode, an image sensing circuit, and a light-emitting driving circuit. The photodiode is disposed on the second surface of the wafer substrate. The image sensing circuit is disposed in the wafer substrate and is electrically connected to the photodiode to drive the photodiode. The light-emitting driving circuit is disposed in the wafer substrate, and is electrically connected to the multiple pins of the light-emitting module via multiple connection units on the first surface of the wafer substrate to drive the light-emitting module.
IMAGE SENSOR, LEVEL SHIFTER CIRCUIT, AND OPERATION METHOD THEREOF
An image sensor, a level shifter circuit, and an operation method thereof are provided. The image sensor includes a pixel circuit and a pixel driving circuit. The pixel driving circuit includes first, second, third, fourth, fifth, and sixth transistors. A first terminal of the first transistor is coupled to a first voltage. A first terminal of the second transistor is coupled to the first voltage, and a control terminal of the second transistor is coupled to a control terminal of the first transistor and a second terminal of the first transistor. A first terminal of the third transistor is coupled to the second terminal of the first transistor, and a second terminal of the third transistor is coupled to a ground voltage. A first terminal of the fourth transistor is coupled to a second terminal of the second transistor and an output terminal.
CHIP WITH AUTOMATIC CLOCK SIGNAL CORRECTION AND AUTOMATIC CORRECTION METHOD
Disclosed are a chip with automatic clock signal correction and an automatic correction method. The chip includes a transmission interface, an oscillator and a correction logic circuit. The transmission interface provides a first clock signal. The oscillator generates a second clock signal. The correction logic circuit is coupled to the oscillator and the transmission interface, and performs correction operation to count the first clock signal to generate a first clock count value, and count the second clock signal to generate a second clock count value. When the first clock count value is equal to the first count target value, the correction logic circuit stops counting, and calculates a correction value based on the second clock count value and the second count target value. The correction logic circuit outputs the correction value to the oscillator, and the oscillator corrects a frequency of the second clock signal according to the correction value.
IMAGE SENSOR AND IMAGE SENSING METHOD
An image sensor and an image sensing method are provided. The image sensor includes a first pixel circuit, a second pixel circuit, a ramp signal generating circuit, a comparator, and a signal processing circuit. The first pixel circuit has a first floating diffusion node. The second pixel circuit has a second floating diffusion node. The ramp signal generating circuit respectively provides a first ramp signal and a second ramp signal to the first floating diffusion node and the second floating diffusion node during a dark sun detection period. The comparator receives a first node voltage of the first floating diffusion node and a second node voltage of the second floating diffusion node. The signal processing circuit determines whether to output an output signal and determines whether to overwrite a digital value corresponding to a sensing signal according to whether the comparator is triggered.
IMAGE SENSOR AND OPERATION METHOD THEREOF
An image sensor and an operation method thereof are provided. The image sensor includes a first pixel circuit and a ramp signal generator. The first pixel circuit includes a first pixel unit; a first transfer transistor coupled to the first pixel unit and a first floating diffusion node; a first readout transistor coupled to the first floating diffusion node; a first ramp capacitor coupled to the first floating diffusion node and receiving a first ramp signal; and a first reset transistor coupled to the first floating diffusion node and receiving a reset signal. The ramp signal generator is coupled to the first ramp capacitor and configured to provide the first ramp signal. A voltage range or a counting result of the pixel circuit during at least one of a reset period and a readout period has an offset.
IMAGE SENSOR AND IMAGE SENSING METHOD
Disclosed are an image sensor and an image sensing method. The image sensor includes a first pixel circuit. The first pixel circuit includes a first driving transistor, a first selection transistor, a first transfer transistor, a first reset transistor and a first sensing unit. A control terminal of the first selection transistor is used for receiving a first selection signal. A control terminal of the first transmitting transistor is used for receiving a first transmitting signal. The image sensing method includes the following steps: receiving a first reset signal during a reset period through a control terminal of the first reset transistor; and receiving a first ramp signal during a sensing period through a control terminal of the first reset transistor.
IMAGE SENSOR AND IMAGE SENSING METHOD
An image sensor and an image sensing method are provided. A readout circuit outputs a first digital sensing signal according to a floating diffusion node voltage of a first pixel circuit reset after a reset stage and a floating diffusion node voltage of a second pixel circuit reset after the reset stage during a reset signal readout period. The readout circuit outputs a second digital sensing signal according to a sensing result of the first pixel circuit and the floating diffusion node voltage of the second pixel circuit reset after the same reset stage during a sensing signal readout period. The image processing circuit judges whether a digital number of at least one of the first digital sensing signal and the second digital sensing signal is abnormal to decide to keep an original digital number, directly set a pixel value, or reset the second digital sensing signal.
IMAGE SENSOR AND IMAGE SENSING METHOD
An image sensor and an image sensing method are provided. A readout circuit outputs a first digital sensing signal according to a floating diffusion node voltage of a first pixel circuit reset after a reset stage and a floating diffusion node voltage of a second pixel circuit reset after the reset stage during a reset signal readout period. The readout circuit outputs a second digital sensing signal according to a sensing result of the first pixel circuit and the floating diffusion node voltage of the second pixel circuit reset after the same reset stage during a sensing signal readout period. The image processing circuit judges whether a digital number of at least one of the first digital sensing signal and the second digital sensing signal is abnormal to decide to keep an original digital number, directly set a pixel value, or reset the second digital sensing signal.