A solid-state imaging device comprises a photodetecting section, an unnecessary carrier capture section, and a vertical shift register. The unnecessary carrier capture section has carrier capture regions arranged in a region between the photodetecting section and the vertical shift register for respective rows. Each of the carrier capture regions includes a transistor and a photodiode. The transistor has one terminal connected to the photodiode and the other terminal connected to a charge elimination line. The charge elimination line is short-circuited to a reference potential line.

In an imaging array having a plurality of pixel sensors arranged in a plurality of rows and columns, pixel data being read out on column lines of the array, a column line voltage clamp circuit for column lines of the array includes a master voltage clamp circuit coupled to provide a reference voltage clamp level on a reference node, and a slave voltage clamp circuit coupled to each column line in the imaging array, each slave voltage clamp circuit configured to clamp voltage on the column line to a column voltage clamp level derived from the reference voltage level.

The present technology relates to an image processing apparatus, an image processing method, electronic equipment and a program which can remove cyclic noise from an image including the cyclic noise. An estimating unit configured to estimate cyclic noise components included in each image picked up under different exposure conditions for each image is included. The estimating unit estimates the cyclic noise components for each image through operation utilizing mutual relationship between the noise components under the exposure conditions. For example, the cyclic noise is flicker. The mutual relationship between the noise components may be expressed with a shutter function of the exposure conditions in frequency space. The present technology may be applied to an imaging apparatus.

Provided is an AD converter including a first AD converting unit in which pixel columns of a pixel array are divided into at least two groups, and that compares a first ramp signal and a first pixel signal output from a first group of the pixel columns and performs AD conversion on the first pixel signal; and a second AD converting unit that compares a second ramp signal and a second pixel signal output from a second group of the pixel columns and performs AD conversion on the second pixel signal, in which the first ramp signal is a signal of which a level is decreased with a constant slope over time in a D-phase period for detecting a signal level of a pixel signal, and the second ramp signal is a signal of which a level is increased with a constant slope over time in the D-phase period.

Analog-to-digital converter (ADC) circuitry may receive multiple analog signals and output corresponding digital signals. During the conversion process, comparators may receive the analog signals and a ramp waveform and compare the two inputs to generate logic signals. The logic signals correspond to digital signals that are outputted by ADC circuitry. To enable offset distribution capabilities, offset distribution circuitry may be selectively coupled to the inputs of the comparators. The offset distribution circuitry may include switches that couples a voltage supply providing reference voltages to the comparators. The reference voltages may be conveyed via a capacitor to the comparators as offset voltages. The offset voltages may provide may be different for different ADC units to offset power consumption of different ADC units and reduce power surges in power sources coupled to ADC circuitry.

An image pickup apparatus configured to output an image signal based on an optical signal photoelectrically converted by an image pickup element provided with two-dimensionally arranged pixels includes: a clipper configured to limit output voltage of the image signal based on the optical signal; a gain upper limit setter configured to set a gain upper limit to be applied to the optical signal; a determiner configured to determine whether or not a condition to cause occurrence of a smear in a shot image is satisfied; and a controller configured to limit an output voltage of the optical signal by using the clipper when the determiner determines that the condition to cause occurrence of the smear is satisfied, and to inactivate limitation of the output voltage of the optical signal by using the clipper when the determiner determines that the condition to cause occurrence of the smear is not satisfied.

Provided is an AD converter including a first AD converting unit in which pixel columns of a pixel array are divided into at least two groups, and that compares a first ramp signal and a first pixel signal output from a first group of the pixel columns and performs AD conversion on the first pixel signal; and a second AD converting unit that compares a second ramp signal and a second pixel signal output from a second group of the pixel columns and performs AD conversion on the second pixel signal, in which the first ramp signal is a signal of which a level is decreased with a constant slope over time in a D-phase period for detecting a signal level of a pixel signal, and the second ramp signal is a signal of which a level is increased with a constant slope over time in the D-phase period.

The solid-state imaging device includes unit cells each of which and generates a pixel signal corresponding to a light reception amount, vertical signal lines each of which is provided for a corresponding column of the unit cells and transfers the corresponding pixel signal, comparators each of which is provided for corresponding one of the vertical signal lines, and a ramp signal generation circuit that supplies a common ramp signal to the comparators. Each of the comparators includes a differential amplifier circuit that includes a transistor to which the ramp signal or the pixel signal is input, a transistor to which the other of the ramp signal and the pixel signal is input, an output terminal for outputting a signal corresponding to a difference between the ramp signal and the pixel signal, and a voltage generation circuit for reducing fluctuations of charge accumulated in a capacitance component of the transistor.

An image sensor in which a first chip and a second chip are stacked comprises: a pixel unit; output lines each configured to output a pixel signal from the pixel unit; and an analog-digital converter provided for each of the output lines. The analog-digital converter comprises a plurality of sets of the following configuration: reference signal generation units configured to generate a reference signal, a comparison unit configured to compare a signal level of a pixel signal output to one of the output lines with a signal level of the reference signal, a counter configured to count until the signal level of the pixel signal coincides with the signal level of the reference signal compared by the comparison unit. The pixel unit is arranged in the first chip and the analog-digital converter is arranged in the second chip.

A method for implementing H-Banding cancellation in an image sensor starts with a pixel array capturing image data. Pixel array includes a plurality of pixels to generate pixel data signals, respectively. ADC circuitry acquires the pixel data signals. ADC circuitry includes a comparator circuitry. In one embodiment, comparator circuitry 310 includes a plurality of comparators. Comparators included in comparator circuitry compare the pixel data signals, respectively, to a ramp signal received from a ramp generator to generate comparator output signals. Adjacent comparators output signals may be opposite in polarity. Other embodiments are described.