Disclosed are image data acquisition methods and systems that utilizes selective temporal co-adding of detector integration samples to construct improved high-resolution output imagery for arrays with selectable line rates. Configurable TDI arrays are used to construct output imagery of various resolutions dependent upon array commanding, the acquisition geometry, and temporal sampling. The image acquisition techniques may be applied to any optical sensor system and to optical systems with multiple sensors at various relative rotations which enable simultaneous image acquisitions of two or more sensors. Acquired image data may be up-sampled onto a multitude of image grids of various resolution.

A time delay integration image sensor may include a number of charge coupled devices (CCDs) that transfer charge in synchronization with the movement of an object being imaged. To increase the dynamic range of the image sensor, the image sensor may include circuitry configured to non-destructively sample the charge as it is transferred through the charge coupled devices. Floating gates may be included in the image sensor and may have a voltage that is proportional to the charge accumulated under the floating gates. Each floating gate may be coupled to a respective readout circuit in an additional substrate by a metal interconnect layer.

Systems and methods in accordance with embodiments of the invention implement TDI imaging techniques in conjunction with monolithic CCD image sensors having multiple distinct imaging regions, where TDI imaging techniques can be separately implemented with respect to each distinct imaging region. In many embodiments, the distinct imaging regions are defined by color filters or color filter patterns (e.g. a Bayer filter pattern); and data from the distinct imaging regions can be read out concurrently (or else sequentially and/or nearly concurrently). A camera system can include: a CCD image sensor including a plurality of pixels that define at least two distinct imaging regions, where pixels within each imaging region operate in unison to image a scene differently than at least one other distinct imaging region. In addition, the camera system is operable in a time-delay integration mode whereby time delay-integration imaging techniques are imposed with respect to each distinct imaging region.

The present disclosure relates to a solid-state image sensor, driving method, and electronic apparatus, capable of achieving reduction in pixel size and sensitivity improvement. The solid-state image sensor includes a PD configured to convert light into electric charge by photoelectric conversion and to store the electric charge, a first transfer transistor configured to read out the electric charge stored in the photoelectric conversion unit, a multiplication region configured to store temporarily and multiply the electric charge read out through the read-out unit, and a second transfer transistor configured to transfer the electric charge stored in the multiplication region to a conversion unit configured to convert the electric charge into a pixel signal. Then, an intense electric field is generated in the multiplication region to multiply electric charge by the avalanche effect in transferring the electric charge from the multiplication region to an FD portion through the second transfer transistor. The present technology is applicable to, in one example, the stacked CMOS image sensors.

The present disclosure provides a bidirectional TDI line image sensor. The bidirectional TDI line image sensor according to one embodiment of the present invention comprises: a pixel unit, which has N line sensors having M CCDs arranged in a line and being arranged in a scan direction, moves, in the scan direction, charges accumulated in the respective columns of the line sensors, and accumulates the same; and an output unit for parallelly receiving as inputs the charges accumulated in the pixel unit from the respective columns, performing analog-to-digital conversion on and storing the charges, and then sequentially outputting same.

The invention relates to a TDI line detector (1), comprising n TDI lines (Z1-Zn), wherein each TDI line (Z) has m pixels (P), and at least one read-out electronics (11-14), wherein the TDI line detector (1) is subdivided into x submodules (S1-S4), wherein the number of lines (Z) of a submodule (S1-S4) is n/x, wherein a discrete read-out electronics (11-14) is associated with the last line of each submodule (S1-S4), wherein the length (L1) of the read-out electronics (11-14) corresponds to an integer multiple of the length (L2) of a pixel (P), wherein x2 is, wherein the associated pixels (P) of different submodules (S1-S4) are arranged pixel to pixel relative to one another or the submodules (S1-S4) or groups of submodules (S1-S4) are laterally interlinked alternately by half a pixel (P).

Real-time autofocus. In an embodiment, a scanning apparatus includes an imaging sensor, a focusing sensor, an objective lens, and processor(s) configured to analyze image data captured by the imaging and focusing sensors, and move the objective lens. Real-time autofocus during scanning of a sample is achieved by determining a true-Z value for the objective lens for a point on a sample and for each of a plurality of regions on the sample. The true-Z values and/or surfaces calculated therefrom are used to determine a predicted-Z value for an unscanned region of the sample. The objective lens is adjusted to the predicted-Z value at the beginning of the unscanned region. After scanning the region, a true-Z value is determined for the region and compared to the predicted-Z value. A rescan of the region is initiated if the comparison exceeds a predetermined threshold.

Systems and methods related to a structured illumination (SI)-based inspection apparatus are described. The SI-based inspection apparatus may be capable of accurately inspecting an inspection object in real time with high resolution, while reducing the loss of light. Also described are an inspection method, and a semiconductor device fabrication method including the SI-based inspection method. The inspection apparatus may include a light source configured to generate and output a light beam, a phase shifting grating (PSG) configured to convert the light beam from the light source into the SI, a beam splitter configured to cause the SI to be incident on an inspection object and output a reflected beam from the inspection object, a stage capable of moving the inspection object and on which the inspection object is arranged, and a time-delayed integration (TDI) camera configured to capture images of the inspection object by detecting the reflected beam.

In time-delay-and-integrate (TDI) imaging, a charge-couple device (CCD) integrates and transfers charge across its columns. Unfortunately, the limited well depth of the CCD limits the dynamic range of the resulting image. Fortunately, TDI imaging can be implemented with a digital focal plane array (DFPA) that includes a detector, analog-to-digital converter (ADC), and counter in each pixel and transfer circuitry connected adjacent pixels. During each integration period in the TDI scan, each detector in the DFPA generates a photocurrent that the corresponding ADC turns into digital pulses, which the corresponding counter counts. Between integration periods, the DFPA transfers the counts from one column to the next, just like in a TDI CCD. The DFPA also non-destructively transfers some or all of the counts to a separate memory. A processor uses these counts to estimate photon flux and correct any rollovers caused by saturation of the counters.

A solid-state imaging device in an embodiment is a solid-state imaging device including an output circuit configured to amplify signals read out from a plurality of pixels. The solid-state imaging device includes a logic circuit configured to generate operation timing of the output circuit and a delay generation circuit configured to control a delay amount for adjusting a pulse generated by the logic circuit to optimum timing. The delay generation circuit is configured of a first variable delay circuit configured to generate a delay pulse, a reference clock of which is delayed by a reference delay amount, a control circuit configured to control the first variable delay circuit and calculate, as a digital signal, a delay code corresponding to the reference delay amount, and a second variable delay circuit configured to adjust the timing of the pulse using the delay code.