An apparatus includes an image sensor having a plurality of pixels that form regions of interest (ROIs), analog-to-digital converter (ADC) banks, and multiplexers. Each respective multiplexer is electrically connected to (i) a corresponding ADC bank and (ii) a corresponding subset of the ROIs. The apparatus also includes control circuitry configured to obtain a full-resolution image of an environment by electrically connecting, by way of the multiplexers, each respective ADC bank to the associated respective ROI. The control circuitry is also configured to select a particular ROI based on the full-resolution image and obtain a plurality of ROI images of the particular ROI by (i) electrically connecting, to the particular ROI, a first ADC bank associated with the particular ROI and a second ADC bank associated with another ROI and (ii) digitizing pixels of the particular ROI by way of parallel operation of the first and second ADC banks.

Multi-stage auto-zeroing signal amplifiers are deployed within event-shuttering pixels of a quanta image sensor (QIS) pixel array to enable reliable per-pixel reporting of photonic events, down to resolution of a single photon strike, for each of a continuous sequence of sub-microsecond event-detection intervals.

An electronic imaging system for a digital camera or imaging device includes a secondary filter having a plurality of filter openings. Each of the filter openings configured to align with a respective light sensor positioned in a grid of light sensors on a CCD. Light filtering media located in the filter openings is employed to reduce light transmitted to the light sensors to either prevent overloads of the sensors or to calculate a corrected light sensor output from a light sensor positioned adjacent an overloaded light sensor.

Examples of an apparatus are disclosed. In some example, an apparatus may include an array of digital pixel cells, each digital pixel cell including a photodiode and a memory device to store a digital output generated based on charge generated by the photodiode in an exposure period. The apparatus may also include an image processor configured to: receive first digital outputs from the memory devices of a first set of digital pixel cells of the array of digital pixel cells; determine, from the first set of digital pixel cells, a second set of digital pixel cells of which the first digital outputs satisfy one or more pre-determined conditions; identify, based on the second set of digital pixel cells, a third set of digital pixel cells; receive the second digital outputs generated by the third set of digital pixel cells; and perform image processing operations based on the second digital outputs.

The application provides a cross-row time delay integral method, apparatus and camera. The method includes obtaining a first stage integral energy in an i-th target region from an i-th row of a first integral piece domain; transferring the first stage integral energy across rows to an i-th row of a second integral piece domain; obtaining the first stage integral energy and an second stage integral energy accumulated in the i-th target region from the i-th row of the second integral piece domain, after an integration period; outputting an image of the i-th target region containing the first stage integral energy and the second stage integral energy. The application performs cross-row integration through the energy obtained by imaging, the shooting of the target can be carried out in a higher-speed environment, the method can be implemented on the existing photoelectric device, and the method has excellent imaging quality and wide applicability.

A solid-state imaging device includes a photoelectric conversion unit, a light shielding unit and a transfer transistor. The photoelectric conversion unit generates charges by photoelectrically converting light. The light shielding unit is formed by engraving a semiconductor substrate on which the photoelectric conversion unit is formed, so as to surround an outer periphery of the photoelectric conversion unit. The transfer transistor transfers charges generated in the photoelectric conversion unit. During a charge accumulation period in which charges are accumulated in the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a gate electrode of the transfer transistor. During a charge transfer period in which charges are transferred from the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a potential that attracts the charges is supplied to the gate electrode of the transfer transistor.

An imaging device having first and second pixels is described. The first pixel comprises a first transfer transistor, a first reset transistor, a first amplifier transistor and a first select transistor. The first transfer transistor has a first terminal coupled to a reference signal generation circuit. The first reset transistor has a first terminal coupled to the reference signal generation circuit. The first amplifier transistor has a gate coupled to a second terminal of the first reset transistor and a second terminal of the first transfer transistor. The first select transistor is coupled to the first amplifier transistor. The second pixel comprises a first photoelectric conversion element, a second transfer transistor, a second reset transistor, a second amplifier transistor and a second select transistor. The second transfer transistor is coupled to the first photoelectric conversion element. The second reset transistor is configured to receive a first predetermined voltage. The second amplifier transistor is coupled to the second transfer transistor and the second reset transistor. The second select transistor is coupled to the second amplifier transistor.

A counting method, a counting device, and a counting system and a pixel array using the counting device are provided. The counting device includes a storage module, which comprises multiple storage units in cascade interconnection, the multiple storage units store a plurality of cumulative count values, the multiple storage units are configured as at least one group of storage units; an arithmetic module connected to a first group of storage units and a last group of storage units for calculation according to a received count value and an added cumulative count values input through the last group of the storage units so as to obtain a current added cumulative count values of corresponding objects, which is then output to the first group of the storage units in cascade interconnection.

An in-pixel embedded analog image processing system performs analog image computation within an image pixel. In embodiments, each in-pixel processing element includes a photodetector, photodetector control circuitry, analog circuitry configured to process both neighbor-in-space and neighbor-in-time functions for analog data representing an electrical current from the photodetector control circuitry, and a set of north-east-west-south (NEWS) registers, each register interconnected between a unique pair of neighboring in-pixel processing elements to transfer analog data between the pair of neighboring in-pixel processing elements. In embodiments, the in-pixel embedded analog image processing device takes advantage of high parallelism because each pixel has its own processor, and takes advantage of locality of data because all data is located within a pixel or within a neighboring pixel.

An in-pixel embedded analog image processing system performs analog image computation within an image pixel. In embodiments, each in-pixel processing element includes a photodetector, photodetector control circuitry, analog circuitry configured to process both neighbor-in-space and neighbor-in-time functions for analog data representing an electrical current from the photodetector control circuitry, and a set of north-east-west-south (NEWS) registers, each register interconnected between a unique pair of neighboring in-pixel processing elements to transfer analog data between the pair of neighboring in-pixel processing elements. In embodiments, the in-pixel embedded analog image processing device takes advantage of high parallelism because each pixel has its own processor, and takes advantage of locality of data because all data is located within a pixel or within a neighboring pixel.