A solid-state imaging device includes a photoelectric conversion unit, a light shielding unit and a transfer transistor. The photoelectric conversion unit generates charges by photoelectrically converting light. The light shielding unit is formed by engraving a semiconductor substrate on which the photoelectric conversion unit is formed, so as to surround an outer periphery of the photoelectric conversion unit. The transfer transistor transfers charges generated in the photoelectric conversion unit. During a charge accumulation period in which charges are accumulated in the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a gate electrode of the transfer transistor. During a charge transfer period in which charges are transferred from the photoelectric conversion unit, a potential that repels the charges is supplied to the light shielding unit and a potential that attracts the charges is supplied to the gate electrode of the transfer transistor.

An electronic device that includes a vision system carried by a bracket assembly is disclosed. The vision system may include a first camera module that captures an image of an object, a light emitting element that emits light rays toward the object, and a second camera module that receives light rays reflected from the object. The light rays may include infrared light rays. The bracket assembly is designed not only carry the aforementioned modules, but to also maintain a predetermined and fixed separation between the modules. The bracket assembly may form a rigid, multi-piece bracket assembly to prevent bending, thereby maintaining the predetermined separation. The electronic device may include a transparent cover designed to couple with a housing. The transparent cover includes an alignment module designed to engage a module and provide a moving force that aligns the bracket assembly and the modules to a desired location in the housing.

A TDI scanner including a dynamically programmable focal plane array including a two-dimensional array of detectors arranged in a plurality of columns and a plurality of rows, the array being divided into a plurality of banks separated from one another by gap regions, each bank including a plurality of sub-banks, and each sub-bank including at least one row of detectors, a ROIC coupled to the focal plane array and configured to combine in a TDI process outputs from detectors in each column of detectors in each sub-bank, and a controller configured to program the focal plane array to selectively and dynamically set characteristics of the focal plane array, the characteristics including a size and a location within the two-dimensional array of each of the plurality of sub-banks and the gap regions, the size corresponding to a number of rows of detectors included in the respective sub-bank or gap region.

A first pixel comprises a first transfer transistor, a first reset transistor, a first amplifier transistor and a first select transistor. The first transfer transistor has a first terminal coupled to a reference signal generation circuit. The first reset transistor has a first terminal coupled to the reference signal generation circuit. The first amplifier transistor has a gate coupled to a second terminal of the first reset transistor and a second terminal of the first transfer transistor. The first select transistor is coupled to the first amplifier transistor. A second pixel comprises a first photoelectric conversion element, a second transfer transistor coupled to the first photoelectric conversion element, a second reset transistor configured to receive a first predetermined voltage, a second amplifier transistor coupled to the second transfer transistor and the second reset transistor, and a second select transistor coupled to the second amplifier transistor.

An image capturing apparatus includes M detection elements, a readout circuit, and a control pulse providing circuit. Each of the M detection elements includes a detection pixel configured to detect incidence of a photon and a generation circuit configured to generate a readout request and data based on the detection of the photon in the detection pixel. The readout circuit is configured to receive the readout request and the data from each of the M detection elements. The control pulse providing circuit is configured to provide a control pulse to the M detection elements and the readout circuit. The readout circuit determines the generation circuit corresponding to the readout request and a generation timing at which the readout request is generated, based on a counter value of the time counter and the number of delay cycles included in the data corresponding to the received readout request.

An image capturing apparatus includes M detection elements, a readout circuit, and a control pulse providing circuit. Each of the M detection elements includes a detection pixel configured to detect incidence of a photon and a generation circuit configured to generate a readout request and data based on the detection of the photon in the detection pixel. The readout circuit is configured to receive the readout request and the data from each of the M detection elements. The control pulse providing circuit is configured to provide a control pulse to the M detection elements and the readout circuit. The readout circuit determines the generation circuit corresponding to the readout request and a generation timing at which the readout request is generated, based on a counter value of the time counter and the number of delay cycles included in the data corresponding to the received readout request.

A solid-state image pickup device according to an embodiment is a solid-state image pickup device including a first pixel row, a second pixel row, and a third pixel row that are arranged in a horizontal direction. In the solid-state image pickup device, a first control pulse for transferring charges of first accumulation portions of the fourth and sixth CCD registers in a vertical direction perpendicular to the horizontal direction and a second control pulse for transferring charges of second accumulation portions of the fourth and sixth CCD registers in the horizontal direction are input to the fourth and sixth CCD registers such that an Hi period of the first control pulse and an Hi period of the second control pulse do not overlap each other in a timing period in which charges accumulated in the first, second, and third pixel rows are transferred.

A semiconductor device capable of performing authentication in a short time can be provided. The semiconductor device includes a light-emitting unit and an imaging unit. The imaging unit includes a row driver circuit, and the row driver circuit includes first to m latch circuits (m is an integer greater than or equal to 2) and first to m register circuits. A first start pulse signal is input to a first latch circuit and second start pulse signals are input to first to m latch circuits. Scan signals output from the first to (m1)-th register circuits are input to the second to m-th latch circuits, respectively. The first latch circuit has a function of outputting one of the first start pulse signal and the second start pulse signal to the first register circuit on the basis of data held, and the second to m-th latch circuits have a function of outputting one of the scan signal and the second start pulse signal to the second to m-th register circuits on the basis of data held.

A semiconductor device capable of performing authentication in a short time can be provided. The semiconductor device includes a light-emitting unit and an imaging unit. The imaging unit includes a row driver circuit, and the row driver circuit includes first to m latch circuits (m is an integer greater than or equal to 2) and first to m register circuits. A first start pulse signal is input to a first latch circuit and second start pulse signals are input to first to m latch circuits. Scan signals output from the first to (m1)-th register circuits are input to the second to m-th latch circuits, respectively. The first latch circuit has a function of outputting one of the first start pulse signal and the second start pulse signal to the first register circuit on the basis of data held, and the second to m-th latch circuits have a function of outputting one of the scan signal and the second start pulse signal to the second to m-th register circuits on the basis of data held.

High dynamic range (HDR) images are generated on the basis of a plurality of images obtained by non-destructive reading of an image sensor, called NDRO images. An HDR image generation method includes: the determination of a criterion of desired quality for the HDR image; at least two non-destructive readings of the sensor delivering at least two successive NDRO images; the selection, as a function of the criterion of desired quality, of the first and of the last NDRO image to be used to generate the HDR image; the generation of the HDR image on the basis of information extracted from a series of successive NDRO images starting with the first and terminating with the last NDRO image to be used; the storage of a single image at one and the same time throughout the entire HDR generation phase.