A charge-coupled device (CCD) image sensor is provided. The CCD image sensor may include an array of photosensors that transfer charge to multiple vertical CCD shift registers, which then in turn transfer the charge to a horizontal CCD shift register. The horizontal CCD shift register then feeds an output buffer circuit. The output buffer circuit can include multiple output stages, each of which can include a source-follower transistor coupled in series with a current sink transistor and at least one cascode transistor. The current sink transistor may have its gate terminal shorted to ground. In one arrangement, the cascode transistor has a gate terminal that receives a non-zero bias voltage. In another arrangement, the cascode transistor has a gate terminal that is also shorted to ground and operates in depletion mode.

A method of binning charges in a charge coupled device (CCD) image sensor is described. The frequency at which an HCCD in the CCD image sensor is clocked may be a multiple of the frequency at which a summing element coupled to the end of the HCCD is clocked, such that charges may be binned at a gate within the HCCD or at the summing element before being read out. The clock signal for the summing element may have a 50% duty cycle in order to provide additional time for charge to flow across an output gate to a floating diffusion node in an output stage of the CCD image sensor. For cases where the HCCD clock frequency is more than twice the summing element clock frequency, charges may be binned at the summing element. Otherwise, charges may be binned at another gate within the HCCD.

Each of pixels disposed in a matrix form on a substrate includes a photoelectric conversion unit that converts incident light into a signal charge, a reading electrode that reads the signal charge from the photoelectric conversion unit, and a vertical transfer electrode that constitutes a vertical transfer unit. A plurality of first pixels, and a plurality of second pixels disposed adjacent to the first pixels are alternately disposed for each row, and also alternately disposed for each column to form a checkered pattern. The reading electrode of each of the pixels is disposed such that a plurality of signal charges read from the identical photoelectric conversion unit contain a dark current generated under the common reading electrode.

A multimode interline charge coupled device having an array of light sensitive pixels, each configured to accumulate photocharge responsive to light incident on the pixel, and a controller configured to allocate a first portion of the pixels to accumulate photocharge responsive to light from a scene during a plurality of exposure periods and allocate a second portion of the pixels to store photocharge accumulated by pixels in the first portion to provide a plurality of images of the scene greater than two.

A pixel array uses two sets of pixels to provide accurate exposure control. One set of pixels provide continuous output signals for automatic light control (ALC) as the other set integrates and captures an image. ALC pixels allow monitoring of multiple pixels of an array to obtain sample data indicating the amount of light reaching the array, while allowing the other pixels to provide proper image data. A small percentage of the pixels in an array is replaced with ALC pixels and the array has two reset lines for each row; one line controls the reset for the image capture pixels while the other line controls the reset for the ALC pixels. In the columns, at least one extra control signal is used for the sampling of the reset level for the ALC pixels, which happens later than the sampling of the reset level for the image capture pixels.

A pixel array uses two sets of pixels to provide accurate exposure control. One set of pixels provide continuous output signals for automatic light control (ALC) as the other set integrates and captures an image. ALC pixels allow monitoring of multiple pixels of an array to obtain sample data indicating the amount of light reaching the array, while allowing the other pixels to provide proper image data. A small percentage of the pixels in an array is replaced with ALC pixels and the array has two reset lines for each row; one line controls the reset for the image capture pixels while the other line controls the reset for the ALC pixels. In the columns, at least one extra control signal is used for the sampling of the reset level for the ALC pixels, which happens later than the sampling of the reset level for the image capture pixels.

The present disclosure relates to a semiconductor device enabling to suppress waste of energy consumption. There is provided a semiconductor device including: an input unit configured to input a charge; a memory unit configured to collect and accumulate a charge from the input unit; and an output unit configured to detect and output a charge accumulated in the memory unit. The memory unit includes a transfer unit to which a plurality of pairs of a gate unit and an accumulation unit is connected, the gate unit selects the accumulation unit that accumulates a charge, the transfer unit transfers a charge from the input unit to the accumulation unit selected by the gate unit, the accumulation unit accumulates a charge transferred from the transfer unit, and the transfer unit transfers a charge accumulated in the accumulation unit selected by the gate unit, to the output unit. The present disclosure can be applied to, for example, an analog memory device.

The present disclosure relates to a semiconductor device enabling to suppress waste of energy consumption. There is provided a semiconductor device including: an input unit configured to input a charge; a memory unit configured to collect and accumulate a charge from the input unit; and an output unit configured to detect and output a charge accumulated in the memory unit. The memory unit includes a transfer unit to which a plurality of pairs of a gate unit and an accumulation unit is connected, the gate unit selects the accumulation unit that accumulates a charge, the transfer unit transfers a charge from the input unit to the accumulation unit selected by the gate unit, the accumulation unit accumulates a charge transferred from the transfer unit, and the transfer unit transfers a charge accumulated in the accumulation unit selected by the gate unit, to the output unit. The present disclosure can be applied to, for example, an analog memory device.

A method of clocking an image sensor which eliminates well bounce effects caused by global current flow in large image sensors during frame readout and line transfer is described. During charge transfer operations in which voltages are applied to VCCD gate contacts that are adjacent to the photodiodes, a compensating voltage may be applied to the lightshield that is associated with, and at least partially formed over the photodiode. Depending on polarity, the compensating lightshield pulse allows holes to locally flow from under the VCCD gates to the photodiode P+ pinning region or vice-versa, and in such a manner to eliminate the global flow of hole current. Lightshields may also be biased during electronic shuttering operations.