The present disclosure relates to a solid-state imaging device and a manufacturing method of the same, and an electronic apparatus, capable of more reliably suppressing occurrence of color mixing. A trench is formed between PDs so as to be opened to a light receiving surface side of a semiconductor substrate on which a plurality of the PDs, each of which receives light to generate charges, are formed, an insulating film is embedded in the trench and the insulating film is laminated on a back surface side of the semiconductor substrate. Then, a light shielding portion is formed so as to be laminated on the insulating film and to have a convex shape protruding to the semiconductor substrate at a location corresponding to the trench. The present technology can be applied to a back surface irradiation type CMOS solid-state imaging device.

Techniques and methods for reducing or preventing latch up in row decoder circuits are disclosed herein. An example apparatus may include an array of pixels, a row address decoder, and control circuitry. The row decode circuit including a plurality of decode circuits, each including at least two transistors having respective body terminals coupled to a first node. The control circuitry including a body biasing circuit coupled to the first node, the body biasing circuit to adaptively provide a bias voltage to the first node in response to an operating state of the imaging system and/or a change in one of two reference voltages based on a control signal provided by a bias control circuit.

The present disclosure relates to a control device, a control method, and a solid-state imaging device that enable a larger number of shutter row addresses to be set at the same time. A vertical selection decoder and a latch circuit set shutter row addresses that identify rows of pixels for which an electronic shutter operation is performed, of pixels arranged in a matrix manner, on the basis of a start address and an end address of the shutter row addresses. The present disclosure is applicable to, for example, a CMOS image sensor that sets the shutter row addresses.

An image sensor including: a pixel array including a plurality of pixels and a row driver configured to drive the pixel array, wherein each of the plurality of pixels includes at least one photodiode, a transmission transistor, a selection transistor, a device isolation structure, and a bulk area, and the row driver is configured to adjust, for each of preset periods, sizes and application timings of a negative voltage applied to the device isolation structure and a bulk control voltage applied to the bulk area while a first pixel is driven.

The photoelectric conversion device includes a pixel. The pixel includes a photoelectric conversion unit and a signal processing circuit. The photoelectric conversion unit includes an avalanche diode that multiplies charge generated by an incident of photon by avalanche multiplication, and outputting a first signal in accordance with the incident of photon. The signal processing circuit includes a logic circuit that outputs a third signal in response to the first signal and a second signal. The signal processing circuit includes a first element having a first withstand voltage and a second element having a second withstand voltage lower than the first withstand voltage, and is configured such that the first signal is input to the first element and the second signal is input to the second element.

The present technology relates to a solid-state imaging element configured so that pixels can be more reliably separated, a method for manufacturing the solid-state imaging element, and an electronic apparatus. The solid-state imaging element includes a photoelectric converter, a first separator, and a second separator. The photoelectric converter is configured to perform photoelectric conversion of incident light. The first separator configured to separate the photoelectric converter is formed in a first trench formed from a first surface side. The second separator configured to separate the photoelectric converter is formed in a second trench formed from a second surface side facing a first surface. The present technology is applicable to an individual imaging element mounted on, e.g., a camera and configured to acquire an image of an object.

In one example, an imaging device including a plurality of pixel circuits, a first control line, a second control line, a first voltage supply line, a second voltage supply line, a first light-receiving element, and a diagnosis unit is disclosed. The pixel circuits each include a first terminal, a second terminal, a third terminal, an accumulation unit, a first transistor, a second transistor, and an output unit. The first transistor is couples the third terminal to the accumulation unit on the basis of a voltage of the first terminal. The second transistor supplies a predetermined voltage to the accumulation unit on the basis of a voltage of the second terminal. The output unit outputs a signal corresponding to a voltage in the accumulation unit.

A light reception element and an electronic apparatus in which leakage current can be reduced to decrease current consumption are provided. The light reception element includes a pixel array section. The pixels each include two taps that detect an electric charge obtained through photoelectric conversion by a photoelectric conversion section. A flat region in each pixel, except the two taps and a pixel transistor region, includes a tap peripheral region and a pixel transistor neighboring region. In the tap peripheral region, an embedded oxide film is formed on a surface opposite to a light incident surface of a substrate, and a first semiconductor region is formed on the light incident surface side of the embedded oxide film. In the pixel transistor neighboring region, a second semiconductor region is formed. The present technology is applicable to a light reception element that carries out ranging, for example.

An electronic device includes a reset circuit and a first image sensing circuit. The reset circuit is used to receive a reset signal and includes a plurality of transistors. The first image sensing circuit is coupled to the reset circuit and includes a photodiode, a first transistor and a second transistor. The photodiode has a first terminal. The first transistor has a first terminal coupled to the first terminal of the photodiode, and a second terminal. The second transistor has a first terminal coupled to the second terminal of the first transistor, and a second terminal configured to receive a row selection signal.

An image sensor having rows and columns of image pixels may include row control circuitry that controls voltages that are sent to each row of the image pixels. The row control circuitry may include booster circuitry that converts a positive power supply voltage (such as 2.8V) to voltages that are negative or otherwise less than the positive power supply voltage and/or greater than the positive power supply voltage. The booster circuitry may have a plurality of switches that control an input to an amplifier, thereby allowing the circuitry to produce any desired voltage in a given range. The booster circuitry output may be shared between multiple rows of the image pixels, and the produced boosted circuitry may be fed to any desired one or more of the rows of image pixels.