A solid-state imaging device is capable of simplifying the pixel structure to reduce the pixel size and capable of suppressing the variation in the characteristics between the pixels when a plurality of output systems is provided. A unit cell includes two pixels. Upper and lower photoelectric converters and, transfer transistors and connected to the upper and lower photoelectric converters, respectively, a reset transistor, and an amplifying transistor form the two pixels. A full-face signal line is connected to the respective drains of the reset transistor and the amplifying transistor. Controlling the full-face signal line, along with transfer signal lines and a reset signal line, to read out signals realizes the simplification of the wiring in the pixel, the reduction of the pixel size, and so on.

A photoelectric conversion device according to one embodiment includes: a first substrate including a pixel that includes a photoelectric conversion element; and a second substrate including a first control unit that includes a first signal processing unit configured to process a signal from the pixel, the second substrate being stacked together with the first substrate. The signal from the pixel is output to a second signal processing unit disposed at a position different from a position of the first signal processing unit, a path through which the signal from the pixel is output to the first signal processing unit is different from a path through which the signal from the pixel is output to the second signal processing unit, and the first control unit is configured to control the pixel on the basis of the signal processed by the first signal processing unit.

A high-accurate imaging increased in time resolution can be made. The camera device is provided with a plurality of pixels that include a light-receiving surface embedded region to convert incident light into charges, a charge accumulation region to accumulate the charges, and a gate electrode to control the charges to be transferred from the light-receiving surface embedded region to the charge accumulation region, and are one-dimensionally arranged in each of a plurality of columns, a timing generation circuit which generates a control pulse voltage to be applied to the gate electrode, and a correction circuit unit which is provided in accordance with each of a plurality of columns of the pixels, delays the control pulse voltage in a variable time, and applies the control pulse voltage to the gate electrodes of the plurality of pixels belonging to a column corresponding to the control pulse voltage.

The present invention relates to an optical biometric sensor comprising: a read-out circuitry controllable for converting analog sensing signals to digital signals, the analog sensing signals being indicative of an image acquired by an image sensor comprising an array of photodetectors; and a timing circuitry configured to control the read-out circuitry to provide digital signals based on a present data transfer capacity on a data transfer bus configured to transfer data indicative of the digital signals from the optical biometric sensor to a host device.

A solid-state imaging device including: a pixel array unit in which a plurality of pixels outputting an analog pixel signal are arranged in a two-dimensional matrix form; a ramp signal generation unit configured to generate and output a ramp wave; a clock generation unit configured to generate and output multiphase clocks; and a signal-processing unit, wherein the signal-processing unit including: a plurality of analog-to-digital conversion circuits, and a plurality of repeater circuits, wherein each of the plurality of analog-to-digital conversion circuits includes: a comparison unit, and a latch unit, wherein each of the plurality of the analog-to-digital conversion circuits outputs the digital value according to the state of the phase held by each latch circuit, and wherein each of the plurality of the repeater circuits corresponding to the same set are arranged side by side, and the repeater circuits are connected in series.

A stereoscopic image capture device includes a first image sensor, a second image sensor, a first frame timer, and a second frame timer. The first and second frame timers are different frame timers. The first image sensor includes a first plurality of rows of pixels. The second image sensor includes a second plurality of rows of pixels. The first and second image sensors can be separate devices or different areas of a sensor region in an integrated circuit. The first frame timer is coupled to the first image sensor to provide image capture timing signals to the first image sensor. The second frame timer coupled to the second image sensor to provide image capture timing signals to the second image sensor.

An image sensor may include a pixel array, row control circuitry, and column readout circuitry. The row control circuitry may operate the pixel array in a global shutter mode of operation. In particular, timing control circuitry may provide global timing clock signals associated with a global photodiode reset event and a global photodiode charge transfer event to row driver circuitry providing control signals to each row in the array. Each driver circuitry may include a time delay circuit that delays the global timing clock signal by different amounts across the rows. Therefore, these global events may be offset on a per-row or per-row group basis, thereby mitigating power surges associated with global events. Further, by offsetting the global photodiode reset and charge transfer events using the same delay for a given row, the same global integration time may be preserved across different rows.

A monolithic sensor for detecting infrared and visible light according to an example includes a semiconductor substrate and a semiconductor layer coupled to the semiconductor substrate. The semiconductor layer includes a device surface opposite the semiconductor substrate. A visible light photodiode is formed at the device surface. An infrared photodiode is also formed at the device surface and in proximity to the visible light photodiode. A textured region is coupled to the infrared photodiode and positioned to interact with electromagnetic radiation.

A monolithic sensor for detecting infrared and visible light according to an example includes a semiconductor substrate and a semiconductor layer coupled to the semiconductor substrate. The semiconductor layer includes a device surface opposite the semiconductor substrate. A visible light photodiode is formed at the device surface. An infrared photodiode is also formed at the device surface and in proximity to the visible light photodiode. A textured region is coupled to the infrared photodiode and positioned to interact with electromagnetic radiation.

A high dynamic range imaging pixel may include a photodiode that generates charge in response to incident light. When the generated charge exceeds a first charge level, the charge may overflow through a first transistor to a first storage capacitor. When the generated charge exceeds a second charge level that is higher than the first charge level, the charge may overflow through a second transistor. The charge that overflows through the second transistor may alternately be coupled to a voltage supply and drained or transferred to a second storage capacitor for subsequent readout. Diverting more overflow charge to the voltage supply may increase the dynamic range of the pixel. The amount of charge diverted to the voltage supply may therefore be updated to control the dynamic range of the imaging pixel.