An image sensor supporting a full resolution mode and a crop mode, the image sensor including: a pixel array including a plurality of pixels configured to generate a pixel signal by sensing an object; an analog-to-digital converter configured to convert the pixel signal into a digital signal and including a plurality of metal lines; a bias generator configured to apply a bias voltage to the plurality of metal lines; and a bias controller including: a first transistor configured to activate all of the plurality of metal lines based on a first control signal; and a second transistor configured to activate a first metal line for the crop mode among the plurality of metal lines based on a second control signal.

A pixel arrangement comprises a photodiode, a circuit node, a transfer transistor coupled to the photodiode and to the circuit node, an amplifier with an input coupled to the circuit node, a first and a second capacitor, a first transistor coupled to an output of the amplifier and to the first capacitor, a second transistor coupled to the first transistor and to the second capacitor, and a coupling transistor coupled to the circuit node and to the second capacitor.

Conventional SRAM sense-amplifiers are replaced by small-footprint keeper circuits that enable single-ended SRAM readout without bitline precharge, simplifying and relaxing the timing of SRAM cell access and bitline sampling operations and thus enabling potentially faster readout operation and/or lower bit error rate.

An image sensor including: first and second capacitors; a first transistor between a photodiode and a floating diffusion node, and receiving a transfer signal; a second transistor between a first power terminal and the floating diffusion node and receiving a reset signal; a third transistor between a second power terminal and a first node and having a gate connected to the floating diffusion node; a fourth transistor between the first node and a column line and receiving a precharge signal; a fifth transistor between the first capacitor and a feedback node and receiving a first sampling signal; a sixth transistor between the second capacitor and feedback node and receiving a second sampling signal; a seventh transistor between the first node and feedback node and receiving a first switch signal; and an eighth transistor between the floating diffusion and feedback nodes and receiving a second switch signal.

A photoelectric conversion apparatus includes an effective pixel circuit, a reference pixel circuit, a signal output unit, and a comparison unit. The effective pixel circuit includes a photoelectric conversion unit, and is configured to be controlled by using a control line and to output a digital signal based on electric charges generated by the photoelectric conversion unit. The reference pixel circuit includes a holding unit for holding the digital signal. The reference pixel circuit is configured to be controlled by using the control line together with the effective pixel circuit. The signal output unit is configured to output a signal to the holding unit so that a first digital signal with a predetermined value is held by the holding unit. The comparison unit is configured to compare the first signal with the digital signal output from the holding unit controlled to hold the first digital signal.

Noise is reduced in a solid-state image capturing element provided with an ADC for each column. An analog-to-digital converter increases or decreases an analog signal using an analog gain selected from among a plurality of analog gains, and converts the increased or decreased analog signal to a digital signal. An input switching section inputs, as the analog signal, one of a test signal having a predetermined level and a pixel signal to the analog-to-digital converter. In a case where a test signal is inputted, a correction value calculation section obtains, from the analog signal and the digital signal, a correction value for correcting an error in the selected analog gain, and outputs the correction value. A correction section, when inputted with the pixel signal after the correction value is outputted, corrects the digital signal using the correction value.

An image sensing device includes a first test block, a second test block, and a readout block. The first test block includes a plurality of first image sensing pixels structured to convert incident light carrying an image into a first pixel signal indicative of the image, and a first heating element structured to transmit heat to the first image sensing pixels. The second test block includes a plurality of second image sensing pixels that each include a light blocking structure to be shielded from receiving incident light to generate a second pixel signal without being directly exposed to the incident light, and a second heating element structured to transmit heat to the second image sensing pixels. The readout block processes the first pixel signal output from the first test block and the second pixel signal output from the second test block.

A solid-state imaging device includes: pixels disposed in a matrix of pixel rows and pixel columns; control wires provided for the pixel rows or the pixel columns, and each connected to at least two pixels out of the pixels, the at least two pixels being included in one of the pixel rows or the pixel columns for which the control wire is provided; drive circuits that are provided for the control wires, each include buffer elements in at least two stages, and each output a control signal to one of the control wires for which the drive circuit is provided, the buffer elements in the at least two stages being connected in series; and a first wire that short-circuits output wires of the buffer elements in one of the at least two stages in at least two of the plurality of drive circuits.

An image sensor may include: a pixel array including a plurality of pixels; and a timing controller configured to control the pixel array according to an operation mode of the pixel array. The operation mode may be any one of a first mode in which the plurality of pixels operate according to a global shutter method and a second mode in which the plurality of pixels operate according to a dual conversion gain method.

Techniques, systems, architectures, and methods for reducing peak power during an Analog-to-Digital Conversion (ADC) process, in embodiments on a Focal Plane Array (FPA).