H04N25/75

Scalable readout integrated circuit architecture with per-pixel automatic programmable gain for high dynamic range imaging
11570392 · 2023-01-31 · ·

An imager device includes a pixel sensor configured to receive and convert incident radiation into a pixel signal and a readout circuit configured to receive the pixel signal from the pixel sensor, generate a received signal strength indicator (RSSI) value based on the pixel signal, and generate a digital signal based on the RSSI value and the pixel signal.

Solid-state imaging device and method for driving the same, and electronic apparatus
11716554 · 2023-08-01 · ·

The present technology relates to a solid-state imaging device, method for driving the same, and electronic apparatus capable of avoiding an occurrence of a blackout in low-speed read-out. The solid-state imaging device includes a pixel array unit in which a plurality of pixels is two-dimensionally arranged in a matrix, and a control unit that exposes all pixels of the pixel array unit at a same exposure timing and performs thinned read-out 2(N−1) times in which all the pixels are thinned to 1/N, so as to read electric charge in all the pixels of the pixel array unit, the electric charge being generated at the same exposure timing. The present technology can be applied to, for example, a solid-state imaging device, or the like, incorporated in an imaging device.

Solid-state imaging device and method for driving the same, and electronic apparatus
11716554 · 2023-08-01 · ·

The present technology relates to a solid-state imaging device, method for driving the same, and electronic apparatus capable of avoiding an occurrence of a blackout in low-speed read-out. The solid-state imaging device includes a pixel array unit in which a plurality of pixels is two-dimensionally arranged in a matrix, and a control unit that exposes all pixels of the pixel array unit at a same exposure timing and performs thinned read-out 2(N−1) times in which all the pixels are thinned to 1/N, so as to read electric charge in all the pixels of the pixel array unit, the electric charge being generated at the same exposure timing. The present technology can be applied to, for example, a solid-state imaging device, or the like, incorporated in an imaging device.

Electric shaver with imaging capability
11716523 · 2023-08-01 · ·

System and method for improving the shaving experience by providing improved visibility of the skin shaving area. A digital camera is integrated with the electric shaver for close image capturing of shaving area, and displaying it on a display unit. The display unit can be integral part of the electric shaver casing, or housed in a separated device which receives the image via a communication channel. The communication channel can be wireless (using radio, audio or light) or wired, such as dedicated cabling or using powerline communication. A light source is used to better illuminate the shaving area. Video compression and digital image processing techniques are used for providing for improved shaving results. The wired communication medium can simultaneously be used also for carrying power from the electric shaver assembly to the display unit, or from the display unit to the electric shaver.

Electric shaver with imaging capability
11716523 · 2023-08-01 · ·

System and method for improving the shaving experience by providing improved visibility of the skin shaving area. A digital camera is integrated with the electric shaver for close image capturing of shaving area, and displaying it on a display unit. The display unit can be integral part of the electric shaver casing, or housed in a separated device which receives the image via a communication channel. The communication channel can be wireless (using radio, audio or light) or wired, such as dedicated cabling or using powerline communication. A light source is used to better illuminate the shaving area. Video compression and digital image processing techniques are used for providing for improved shaving results. The wired communication medium can simultaneously be used also for carrying power from the electric shaver assembly to the display unit, or from the display unit to the electric shaver.

Image sensor with high conversion gain (HCG) mode and low conversion gain (LCG) mode

An image sensor includes a pixel configured to operate in a high conversion gain (HCG) mode and a low conversion gain (LCG) mode during a readout period, and a correlated double sampling (CDS) circuit configured to generate a comparison signal based on a ramp signal and a pixel voltage received from the pixel, wherein the CDS circuit includes a comparator configured to: receive the pixel voltage through a first input node, receive the ramp signal through a second input node based on an LCG reset signal or an LCG image signal being received as the pixel voltage, and receive the ramp signal through a third input node based on an HCG reset signal or an HCG image signal being received as the pixel voltage; and compare the ramp signal to the pixel voltage, and output the comparison signal corresponding to a comparison result.

Image sensor with high conversion gain (HCG) mode and low conversion gain (LCG) mode

An image sensor includes a pixel configured to operate in a high conversion gain (HCG) mode and a low conversion gain (LCG) mode during a readout period, and a correlated double sampling (CDS) circuit configured to generate a comparison signal based on a ramp signal and a pixel voltage received from the pixel, wherein the CDS circuit includes a comparator configured to: receive the pixel voltage through a first input node, receive the ramp signal through a second input node based on an LCG reset signal or an LCG image signal being received as the pixel voltage, and receive the ramp signal through a third input node based on an HCG reset signal or an HCG image signal being received as the pixel voltage; and compare the ramp signal to the pixel voltage, and output the comparison signal corresponding to a comparison result.

Image sensor with shifted color filter array pattern and bit line pairs

An imaging device includes groupings of photodiodes having four photodiodes. A transfer transistor is between each photodiode and a floating diffusion. Each floating diffusion is coupled to up to two photodiodes per grouping at a time through transfer transistors. A buffer transistor is coupled to each floating diffusion. The buffer transistors may be in a first or second grouping of buffer transistors. A first bit line is coupled to up to two buffer transistors of the first grouping and a second bit line is coupled to up to two buffer transistors of the second grouping of buffer transistors at a time. A color filter array including a plurality of groupings of color filters is disposed over respective photodiodes of the photodiode array, wherein each grouping of color filters includes four color filters having a same color, wherein each grouping of color filters overlaps two groupings of photodiodes.

Image sensor with shifted color filter array pattern and bit line pairs

An imaging device includes groupings of photodiodes having four photodiodes. A transfer transistor is between each photodiode and a floating diffusion. Each floating diffusion is coupled to up to two photodiodes per grouping at a time through transfer transistors. A buffer transistor is coupled to each floating diffusion. The buffer transistors may be in a first or second grouping of buffer transistors. A first bit line is coupled to up to two buffer transistors of the first grouping and a second bit line is coupled to up to two buffer transistors of the second grouping of buffer transistors at a time. A color filter array including a plurality of groupings of color filters is disposed over respective photodiodes of the photodiode array, wherein each grouping of color filters includes four color filters having a same color, wherein each grouping of color filters overlaps two groupings of photodiodes.

Image sensor having on-chip compute circuit

In one example, an apparatus comprises: a first sensor layer, including an array of pixel cells configured to generate pixel data; and one or more semiconductor layers located beneath the first sensor layer with the one or more semiconductor layers being electrically connected to the first sensor layer via interconnects. The one or more semiconductor layers comprises on-chip compute circuits configured to receive the pixel data via the interconnects and process the pixel data, the on-chip compute circuits comprising: a machine learning (ML) model accelerator configured to implement a convolutional neural network (CNN) model to process the pixel data; a first memory to store coefficients of the CNN model and instruction codes; a second memory to store the pixel data of a frame; and a controller configured to execute the codes to control operations of the ML model accelerator, the first memory, and the second memory.