An image sensing device includes a first test block, a second test block, and a readout block. The first test block includes a plurality of first image sensing pixels structured to convert incident light carrying an image into a first pixel signal indicative of the image, and a first heating element structured to transmit heat to the first image sensing pixels. The second test block includes a plurality of second image sensing pixels that each include a light blocking structure to be shielded from receiving incident light to generate a second pixel signal without being directly exposed to the incident light, and a second heating element structured to transmit heat to the second image sensing pixels. The readout block processes the first pixel signal output from the first test block and the second pixel signal output from the second test block.

A solid state image sensor includes a pixel array, as well as charge-to-voltage converters, reset gates, and amplifiers each shared by a plurality of pixels in the array. The voltage level of the reset gate power supply is set higher than the voltage level of the amplifier power supply. Additionally, charge overflowing from photodetectors in the pixels may be discarded into the charge-to-voltage converters. The image sensor may also include a row scanner configured such that, while scanning a row in the pixel array to read out signals therefrom, the row scanner resets the charge in the photodetectors of the pixels sharing a charge-to-voltage converter with pixels on the readout row. The charge reset is conducted simultaneously with or prior to reading out the signals from the pixels on the readout row.

A first flip-flop outputs a first output signal as a first switch signal that controls a first switch. A second flip-flop outputs a second output signal based on a clock signal and the first output signal. A first inverting circuit generates a first inverted signal obtained by inverting the first output signal. A second AND circuit outputs a signal that is an AND of the first inverted signal and the second output signal, as a second switch signal that controls a second switch.

Imagers and associated devices and systems are disclosed herein. In one embodiment, an imager includes a pixel array and control circuitry operably coupled to the pixel array. The pixel array includes an imaging pixel configured to produce a reset signal and a non-imaging pixel configured to produce a nominal reset signal. The control circuitry is configured to produce an output signal based at least in part on one of (a) the nominal reset signal when distortion at the imaging pixel exceeds a threshold and (b) the reset signal when distortion does not exceed the threshold.

Systems and methods for controlling the parameters of groups of focal planes as focal plane groups in an array camera are described. One embodiment includes a plurality of focal planes, and control circuitry configured to control the capture of image data by the pixels within the focal planes. In addition, the control circuitry includes: a plurality of parameter registers, where a given parameter register is associated with one of the focal planes and contains configuration data for the associated focal plane; and a focal plane group register that contains data identifying focal planes that belong to a focal plane group. Furthermore, the control circuitry is configured to control the imaging parameters of the focal planes in the focal plane groups by mapping instructions that address virtual register addresses to the addresses of the parameter registers associated with focal planes within specific focal plane groups.

A radiation therapy system is configured with fast readout of X-ray images with significantly reduced image lag. A reset phase is included in the process of acquiring an X-ray image to reduce image lag in a subsequently acquired X-ray image. During the reset phase, residual charge is concurrently transferred from multiple arrays of pixel detector elements in an X-ray detector panel. As a result, image lag present in a subsequent X-ray image is minimized or otherwise reduced.

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.

A photon counting device includes a plurality of pixels each including a photoelectric conversion element configured to convert input light to charge, and an amplifier configured to amplify the charge converted by the photoelectric conversion element and convert the charge to a voltage, an A/D converter configured to convert the voltages output from the amplifiers of the plurality of pixels to digital values; and a conversion unit configured to convert the digital value output from the A/D converter to the number of photons by referring to reference data, for each of the plurality of pixels, and the reference data is created based on a gain and an offset value for each of the plurality of pixels.

A solid-state imaging device includes a pixel array unit and a current source array unit. The pixel array unit includes N pixel units arrayed in a first direction. Each pixel unit includes a photodiode and an amplification MOS transistor. The current source array unit includes N current sources. Each current source includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a setting circuit. The setting circuit sets ON/OFF of the third MOS transistor on the basis of a voltage of the signal line, thereby suppressing fluctuations in an amount of current flowing from a Vr supply line to a ground potential supply terminal via a common node and the first MOS transistor.

The invention concerns an image sensor comprising: at least one pixel having a photodiode (PD); a sensing node (SN) coupled to the photodiode via a transfer gate (104); and a further node (AN) coupled to the sensing node (SN) via a first transistor (112); and a control circuit (120) adapted: to apply, during a reset operation of the voltage levels at the sensing node (SN) and further node (AN), a first voltage level (VDD) to a control node of the first transistor (112); and to apply, during a transfer operation of charge from the photodiode (PD) to the sensing node (SN), a second voltage level (VSK) to the control node of the first transistor (112), the second voltage level being lower than the first voltage level and higher than a ground voltage of the pixel.