A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.

An imaging device including: a first imaging cell including a first photoelectric converter that generates a first signal; and a second imaging cell including: a second photoelectric converter that generates a second signal; and a capacitor having a first and second terminal, the first terminal electrically coupled to second photoelectric converter. An area of the first photoelectric converter is greater than an area of the second photoelectric converter in a plan view, the first imaging cell has a first number of saturation charges, and the second imaging cell has a second number of saturation charges, the first number of saturation charges is greater than the second number of saturation charges, and the capacitor has capacitance that causes the second number of saturation charges of the second imaging cell to become greater than the first number of saturation charges of the first imaging cell.

The present technology relates to an imaging element that can reduce noise. The imaging element includes: a photoelectric conversion element; a first amplification element that amplifies a signal from the photoelectric conversion element; a second amplification element that amplifies an output from the first amplification element; an offset element provided between the first amplification element and the second amplification element; a first reset element that resets the first amplification element; and a second reset element that resets the second amplification element. The offset element is a capacitor. A charge is accumulated in the offset element via a feedback loop of an output from the second amplification element, and an offset bias is generated. The present technology can be applied to an imaging element.

The present disclosure relates to a solid-state imaging device and an electronic device that can be provided with phase difference pixels with a lower degree of difficulty in manufacturing.

Provided is a solid-state imaging device including a pixel array unit in which a plurality of pixels is two-dimensionally arrayed, in which the pixel array unit has an array pattern in which a plurality of pixel groups each including neighboring pixels of an identical color is regularly arrayed, and among the plurality of pixel groups arrayed in the array pattern, pixels configuring a light-shielded pixel group are shielded in an identical direction side from light, the light-shielded pixel group being a pixel group including pixels each being shielded in a part of a light incident side from the light. The present technology can be applied to, for example, a CMOS image sensor including pixels for phase difference detection.

A solid-state imaging device capable of performing encryption processing with enhanced security by quite extremely safely generating unique information and performing encryption processing based on the generated unique information. There is provided a solid-state imaging device including a unique information generation unit that generates predetermined analog information, a unique value generation unit that generates a predetermined unique value based on the predetermined analog information, and an encryption processing unit that performs encryption processing using the predetermined unique value, in which the unique value generation unit includes a detection unit that converts the predetermined analog information into digital information, and a unique value calculation unit that calculates the predetermined unique value using the digital information, in which the solid-state imaging device further includes a high-pass filter that passes a high-frequency signal for at least one of the analog information or the digital information.

A solid-state imaging device includes a photoelectric converter, a transfer gate transistor, and an overflow gate transistor. The photoelectric converter is provided in a semiconductor substrate and generates photocharge. The transfer gate transistor is provided at a surface of the semiconductor substrate as a vertical transistor and reads the photocharge stored in the photoelectric converter. The overflow gate transistor is provided at the surface of the semiconductor substrate as a planar transistor and transfers the photocharge overflowing from the photoelectric converter.

A unit pixel includes a first photoelectric conversion unit configured to generate first charges in response to a first incident light, a first transfer transistor connected between the first photoelectric conversion unit and a first node, a connecting transistor connected between a second node and the first node, a second photoelectric conversion unit configured to generate second charges in response to a second incident light, a second transfer transistor connected between a second photoelectric conversion unit and a third node, a switch transistor connected between the third node and the second node, a source follower connected to the first node, a selection transistor connected to the source follower, an overflow transistor connecting the first photoelectric conversion unit and a power supply voltage, and a comparator configured to turn on the overflow transistor.

A unit pixel includes a first photoelectric conversion unit configured to generate first charges in response to a first incident light, a first transfer transistor connected between the first photoelectric conversion unit and a first node, a connecting transistor connected between a second node and the first node, a second photoelectric conversion unit configured to generate second charges in response to a second incident light, a second transfer transistor connected between a second photoelectric conversion unit and a third node, a switch transistor connected between the third node and the second node, a source follower connected to the first node, a selection transistor connected to the source follower, an overflow transistor connecting the first photoelectric conversion unit and a power supply voltage, and a comparator configured to turn on the overflow transistor.

The photoelectric conversion device includes a pixel including a photoelectric conversion unit that outputs a pulse in response to incidence of a photon and a pulse counting unit that counts the pulse. The pulse counting unit includes first and second counters, a selection circuit for selecting a signal input to the first and second counters, and a control unit. The control unit controls the selection circuit to perform a first connection mode in which a counter of a first number of bits is configured by the first and second counters, and a second connection mode in which a counter of a second number of bits smaller than the first number of bits is configured by at least one of the first and second counters. The second connection mode includes a third connection mode in which pulses are counted in parallel by the first and second counters.

The photoelectric conversion device includes a pixel including a photoelectric conversion unit that outputs a pulse in response to incidence of a photon and a pulse counting unit that counts the pulse. The pulse counting unit includes first and second counters, a selection circuit for selecting a signal input to the first and second counters, and a control unit. The control unit controls the selection circuit to perform a first connection mode in which a counter of a first number of bits is configured by the first and second counters, and a second connection mode in which a counter of a second number of bits smaller than the first number of bits is configured by at least one of the first and second counters. The second connection mode includes a third connection mode in which pulses are counted in parallel by the first and second counters.