In an embodiment, a method of reducing resistance-capacitance delay along photodiode transfer lines of an image sensor includes forking a plurality of photodiode transfer lines each into a plurality of sublines coupled together and to a first decoder-driver at a first end of each subline; and distributing selection transistors of a plurality of multiple-photodiode cells among the plurality of sublines. In embodiments, the sublines may be recombined at a second end of the sublines and driven by a second decoder-driver at the second end.

In an embodiment, a method of reducing resistance-capacitance delay along photodiode transfer lines of an image sensor includes forking a plurality of photodiode transfer lines each into a plurality of sublines coupled together and to a first decoder-driver at a first end of each subline; and distributing selection transistors of a plurality of multiple-photodiode cells among the plurality of sublines. In embodiments, the sublines may be recombined at a second end of the sublines and driven by a second decoder-driver at the second end.

An image sensor comprises: a plurality of pixels each having an avalanche photodiode; and a control unit that controls to provide to the avalanche photodiodes of the plurality of pixels a reverse bias voltage that periodically changes.

Photoelectric conversion device includes first substrate having blocks each including photoelectric converters, and second substrate having at least part of processing circuit for reading out signals from the photoelectric converters. The processing circuit drives driving signal lines for driving the photoelectric converters. The driving signal lines include first signal lines each arranged in the first substrate and commonly assigned to at least two blocks arranged in row direction of the blocks and second signal lines each individually assigned to one block of the blocks. The processing circuit includes transmission lines and selection circuits each corresponding to one second signal line of the second signal lines. Each selection circuit selects one driving signal from driving signals supplied to the transmission lines, and supplies the selected driving signal to the corresponding second signal line of the second signal lines.

A device of the disclosure comprises pixels including photoelectric converters generating charge, transistors having nodes receiving signals based on the charge, and transistors supplying reset voltage; and lines along the columns, wherein: in a first period, the node is disconnected from the converter, and signals based on the reset voltage is output from a pixel in a first row to a line, in a second period, signals based on the reset voltage and the charge transferred to the node are output from the pixel in the first row to a line, in a third period, signals based on the charge is output from a pixel in a second row to a line, in a fourth period, signals based on the charge is output from a pixel in a third row to a line, and the first period is prior to the second period, and between the third and fourth periods.

A device of the disclosure comprises pixels including photoelectric converters generating charge, transistors having nodes receiving signals based on the charge, and transistors supplying reset voltage; and lines along the columns, wherein: in a first period, the node is disconnected from the converter, and signals based on the reset voltage is output from a pixel in a first row to a line, in a second period, signals based on the reset voltage and the charge transferred to the node are output from the pixel in the first row to a line, in a third period, signals based on the charge is output from a pixel in a second row to a line, in a fourth period, signals based on the charge is output from a pixel in a third row to a line, and the first period is prior to the second period, and between the third and fourth periods.

A breakdown-avalanche photon sensors array (10) is shown, which is implemented in CMOS technology, wherein the breakdown-avalanche photon sensors array (10) has single photon sensitivity, comprising: a semiconductor substrate (11); and an epitaxial layer (12), which is located above the semiconductor substrate (11); and a breakdown-avalanche photon sensor (13), which is located within the epitaxial layer (12), wherein the breakdown avalanche photon sensor (13) comprises: a guard ring (3) and a quenching element (5), which is electrically connected to the breakdown-avalanche photon sensor (13), wherein the quenching element (5) is configured for quenching the breakdown-avalanche photon sensor (13) after detection of a photon. Furthermore, a digital breakdown-avalanche photon sensor (11), a digital breakdown-avalanche photon sensors array (20)and an digital photomultiplier imager (40) are shown.

A breakdown-avalanche photon sensors array (10) is shown, which is implemented in CMOS technology, wherein the breakdown-avalanche photon sensors array (10) has single photon sensitivity, comprising: a semiconductor substrate (11); and an epitaxial layer (12), which is located above the semiconductor substrate (11); and a breakdown-avalanche photon sensor (13), which is located within the epitaxial layer (12), wherein the breakdown avalanche photon sensor (13) comprises: a guard ring (3) and a quenching element (5), which is electrically connected to the breakdown-avalanche photon sensor (13), wherein the quenching element (5) is configured for quenching the breakdown-avalanche photon sensor (13) after detection of a photon. Furthermore, a digital breakdown-avalanche photon sensor (11), a digital breakdown-avalanche photon sensors array (20)and an digital photomultiplier imager (40) are shown.

An image sensor may include an array of image sensor pixels. Pixel control circuitry may provide control signals to the array of image sensor pixels. The pixel control circuitry may include a plurality of driver units that each generate a control signal for a different set of image sensor pixels. The control signal generated by each of the driver units may be delayed relative to each other. A voltage-controlled delay line may provide delayed outputs to each of the driver units. Delay lock circuitry coupled to the voltage-controlled delay line may fix the delay exhibited across the delay line using corresponding global and local bias voltages provided to each of the inverters in the delay line.

An image sensor may include an array of image sensor pixels. Pixel control circuitry may provide control signals to the array of image sensor pixels. The pixel control circuitry may include a plurality of driver units that each generate a control signal for a different set of image sensor pixels. The control signal generated by each of the driver units may be delayed relative to each other. A voltage-controlled delay line may provide delayed outputs to each of the driver units. Delay lock circuitry coupled to the voltage-controlled delay line may fix the delay exhibited across the delay line using corresponding global and local bias voltages provided to each of the inverters in the delay line.