An image sensor includes a pixel array including a plurality of pixel blocks, each including a light receiving section including unit pixels which share a floating diffusion; a first driving section disposed at one side of the light receiving section and including a reset transistor; and a second driving section disposed adjacent to the first driving section and including a driver transistor, wherein the pixel blocks include a first pixel block and a second pixel block which is adjacent to the first pixel block, and, with respect to a boundary where the first pixel block and the second pixel adjoin each other, the first driving section of the first pixel block has a shape symmetrical to the first driving section of the second pixel block and the second driving section of the first pixel block has a shape asymmetrical to the second driving section of the second pixel block.

The disclosure extends to methods, systems, and computer program products for widening dynamic range within an image in a light deficient environment.

A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a simplified stacked structure and improved operation characteristics includes an upper chip, in which a plurality of pixels are arranged in a two-dimensional array structure, and a lower chip below the upper chip including a logic region having logic circuits and a memory region having embedded therein magnetic random access memory (MRAM) used as image buffer memory for storing image data processed by the logic region.

An imaging device includes: a pixel array including first and second pixels, each pixel including a photoelectric converter converting light into charge and a detection circuit detecting the charge; a first voltage supply circuit supplying a first voltage to the first pixel such that an electric potential of the first electrode is set to a first electric potential at a point of time at which a charge accumulation period for the first pixel starts; a second voltage supply circuit supplying a second voltage to the second pixel such that an electric potential of the first electrode of the second pixel is set to a second electric potential different from the first electric potential at a point of time at which a charge accumulation period for the second pixel starts; and an addition circuit adding together signals generated in the first and second pixels.

A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a simplified stacked structure and improved operation characteristics includes an upper chip, in which a plurality of pixels are arranged in a two-dimensional array structure, and a lower chip below the upper chip including a logic region having logic circuits and a memory region having embedded therein magnetic random access memory (MRAM) used as image buffer memory for storing image data processed by the logic region.

An image sensor having active, peripheral and dummy regions is provided as follows. A dummy through electrode is disposed in the substrate. An active through electrode is disposed in the substrate. An insulation structure in which a color filter is embedded is disposed on the substrate. A dummy bottom electrode is disposed on the insulation structure and connected electrically to the dummy through electrode. An active bottom electrode is disposed on the insulation structure and connected electrically to the active through electrode. A photoelectric conversion layer is disposed on the insulation structure. A top electrode is disposed on the photoelectric conversion layer and the dummy bottom electrode. The top electrode is connected electrically to the dummy bottom electrode. The photoelectric conversion layer is interposed between the top electrode and the active bottom electrode which are separated from each other.

In a solid-state image capturing device, one or more vertical signal lines are disposed along one of columns of a pixel portion, and each of the vertical signal lines is divided into two parts between an upper region and a lower region of the pixel portion. Pixel signals output from a plurality of pixels of the one of the columns are read out to a plurality of column readout circuits through two or more parts of the vertical signal lines including the two parts of the one or more vertical signal lines disposed along the one of the columns. A division position of one vertical signal line among the vertical signal lines disposed in the pixel portion is different from a division position of another vertical signal line among the vertical signal lines in a row direction.

An object of the present invention is to detect a failure of a camera input in a system including a camera or a video transmission path (camera input). An image processor includes a hash derivation circuit having a computing unit that calculates hash values on an input screen and a storage circuit that stores the hash values. The image processor compares the hash values between multiple frames so as to decide whether the screens have changed or stopped. A failure is detected when the screens are stopped.

An image sensor may include an organic photo-sensing device configured to selectively sense first visible light and a photo-sensing device array including a first photo-sensing device configured to selectively sense second visible light, a second photo-sensing device configured to selectively sense third visible light, and a third photo-sensing device configured to selectively sense mixed light of the second visible light and the third visible light. The image sensor may include a color filter array including a first color filter configured to selectively transmit the second visible light, a second color filter configured to selectively transmit the third visible light, and a third color filter configured to transmit mixed light of the second visible light and the third visible light. At least the first photo-sensing device and the second photo-sensing device may be at different depths in a substrate and may be laterally offset from each other.

A substrate has a first surface and a second surface facing each other. A photoelectric conversion region includes a plurality of photoelectric conversion devices provided in the substrate. An interlayered insulating layer is provided on the first surface of the substrate. A plurality of wires is provided on the interlayered insulating layer. An inter-wire insulating layer covers the plurality of wires. A plurality of micro lenses is provided on the second surface of the substrate. A grid pattern is provided in at least one of the interlayered insulating layer and the inter-wire insulating layer. The grid pattern, when viewed in a plan view, overlaps a region between two adjacent photoelectric conversion devices of the plurality of photoelectric conversion devices.