A voltage sensor system for determining an abnormal circuit condition in a multi-layer printed circuit board is disclosed. The printed circuit board has a plurality of layers. One of the layers includes a trace network and a sensor circuit. The sensor circuit includes the trace network and a sensing point. The sensor circuit is coupled between a voltage supply and a ground. A controller is coupled to the sensing point. The controller is operable to determine a voltage of the sensing point and compare the voltage to a threshold value to determine an abnormal circuit condition in the printed circuit board.

A display device including: a display panel; a first substrate attached to a side of the display panel; and a second substrate attached to a side of the first substrate, wherein the display panel includes a first panel test pad and a second panel test pad, the first substrate includes a 1-1 circuit test lead overlapping and connected to the first panel test pad, a 1-2 circuit test lead overlapping and connected to the second panel test pad, a 2-1 circuit test lead overlapping and connected to the second substrate, a 1-1 test lead line connected to the 1-1 circuit test lead, a 1-2 test lead line connected to the 1-2 circuit test lead, and a first test lead line connected to the 2-1 circuit test lead, and the 1-1 test lead line and the 1-2 test lead line are connected to the first test lead line.

A manufacturing method of a carrier structure includes: A build-up circuit layer is formed on a carrier. The build-up circuit layer includes at least one first circuit layer, at least one first dielectric layer, a second circuit layer, a second dielectric layer, and a plurality of conductive vias. The first circuit layer is located on the carrier and includes at least one first pad, which is disposed relative to at least one through hole of the carrier. The first dielectric layer is located on the first circuit layer. The second circuit layer is located on the first dielectric layer and includes at least one second pad. The second dielectric layer is located on the second circuit layer and includes at least one opening exposing the second pad. The conductive via penetrates the first dielectric layer and is electrically connected to the first circuit layer and the second circuit layer.

Provided is a display apparatus including: a display panel including a display area and a peripheral area; a printed circuit board attached to the peripheral area and including a ground portion and a test electrode spaced apart from the ground portion; a connector including a plurality of connector terminals connected to an external control apparatus and electrically connecting the printed circuit board and the external control apparatus to each other; and a cover layer arranged on the printed circuit board and covering at least a part of the printed circuit board. Accordingly, not only the display quality and reliability of the electric characteristics of the display apparatus are improved, but also a loss is reduced and a yield is improved during manufacturing processes.

There is provided a semiconductor apparatus including a memory controller; a CPU; a high-speed communication controller; a memory operation terminal group that includes a plurality of memory operation terminals for inputting a first signal propagating between an external memory group and the memory controller; a high-speed communication terminal group that includes a plurality of high-speed communication terminals for inputting a second signal to the high-speed communication controller; an inspection terminal group that includes a plurality of inspection terminals for acquiring information from the CPU and performing debugging; and a terminal mounting surface at which the memory operation terminal group, the high-speed communication terminal group, and the inspection terminal group are provided, in which at the terminal mounting surface, a first inspection terminal among the plurality of inspection terminals is located between the memory operation terminal group and the high-speed communication terminal group.

Disclosed is a system and method for monitoring a characteristic of an environment of an electronic device. The electronic device may include a printed circuit board and a component. A sensor is placed on the printed circuit board, and may be between the component and the board, and connects to a monitor, or detector. An end user device may be used to store, assess, display and understand the data received from the sensor through the monitor.

A printed circuit board, an in-circuit test structure and a method for producing the in-circuit test structure thereof are disclosed. The in-circuit test structure comprises a via and a test pad. The via passes through the printed circuit board for communicating with an electrical device to be tested on the printed circuit board. The test pad is formed on an upper surface of the printed circuit board and covering the via, wherein a center of the via deviates from a center of the test pad. In the in-circuit test, the accuracy of the test data can be improved by means of the in-circuit test structure provided by the present invention, and thus the reliability of the test result is ensured. Also, the test efficiency of the in-circuit test is improved.

A system on package SoP module includes a printed circuit board (PCB) having a first side and an opposing second side, a first IC attached to the first side, a second IC attached to the second side. The PCB also provides electrical paths for connecting the first IC and the second IC. Conductors by which the second IC is attached to the PCB also allow for electrical testing of the first IC when the SoP is in a system level state.

A multilayer printed circuit having a control circuit including n vias that are connected in series between a first and a second electrical terminal so that an applied electric current passes at least partially through each one of the n vias. The control circuit includes track portions in each one of the layers, each one of the n vias connecting a track portion of one layer to a track portion of another layer. The control circuit includes a measurement device for measuring a potential difference across its terminals, storage for storing a threshold value and a comparator for comparing the potential difference with the threshold value so as to validate the printed circuit when the potential difference is lower than the threshold value.

Some embodiments of the present invention are generally directed to testing connections of a memory device to a circuit board or other device. In one embodiment, a memory device that is configured to facilitate continuity testing between the device and a printed circuit board or other device is disclosed. The memory device includes a substrate and two connection pads that are electrically coupled to one another via a test path. A system and method for testing the connections between a memory device and a circuit board or other device are also disclosed, as are additional techniques for detecting excess temperature and enabling special functionalities using multi-stage connection pads.