A resistor assembly is disclosed and comprises a first conductive trace, a second conductive trace, and a plurality of trimming bridges that electrically couple the first conductive trace to the second conductive trace. The resistor assembly also comprises a thin film resistor electrically coupled to the first conductive trace. The first conductive trace, the second conductive trace, the plurality of trimming bridges, and the thin film resistor are all part of a surface mounted layer of the resistor assembly. The plurality of trimming bridges are each removable to increase a resistance of the thin film resistor.

A conductive trace interconnect tape for use with a printed circuit board or a flexible circuit substrate comprises a top insulating layer, an electrically conductive layer, and a bottom insulating layer. The top insulating layer is formed from electrically insulating material and is configured to provide electrical isolation from electrically conductive objects that are positioned on top of the conductive trace interconnect tape. The electrically conductive layer is positioned underneath the top insulating layer. The electrically conductive layer is formed from electrically conductive material and includes electrical interconnect traces, electrical component pads, or electrically conductive planar portions. The bottom insulating layer is positioned underneath the electrically conductive layer. The bottom insulating layer is formed from electrically insulating material and is configured to provide electrical isolation from electrically conductive objects that are positioned on the printed circuit board or flexible circuit substrate.

Disclosed is an interface circuit, a chip containing an interface circuit and a manufacturing method thereof. The interface circuit includes an I/O processing sub-circuit, a path selection sub-circuit, and at least two I/O ports. The I/O processing sub-circuit, the path selection sub-circuit, and the at least two I/O ports are electrically connected in sequence. The path selected by the path selection sub-circuit can enable a first and a second electrical signal to be transmitted through the I/O ports that are configured to correspond to the ports of the external device through which the first and second electrical signals are transmitted. That is, the path selection sub-circuit can customize the layout of the signal-input/output I/O ports of the interface circuit according to the layout of the ports of the external device.

A method of running a printed circuit board (PCB) trace on a PCB. The PCB comprising a plurality of PCB layers. The method comprising forming a conductive trace on at least one of the plurality of PCB layers; coupling a first portion of the conductive trace to a capacitor formed on at least one of the plurality of PCB layers; coupling a second portion, different from the first portion, of the conductive trace to a conductive material formed within a first via extending through two or more of the plurality of PCB layers; and configurably setting a length of a conductive path of the conductive trace according to a predetermined impedance. The capacitor is separated laterally in a plan view at a first distance from the first via. The length of the conductive trace in the plan view is greater than the first distance. The conductive path of the conductive trace of the length has the predetermined impedance.

Articles, electronic devices and related methods of fabrication interfacing graphene with a gallium liquid metal alloy.

In some embodiments, an interconnectable circuit board may include one or more of the following features: (a) a first electrically conductive pad located on a top of the circuit board, (b) a plated through hole on the conductive pad which passes through the circuit board, (c) a second electrically conductive pad coupled to the plated through hole; the second conductive pad capable of being electrically connected to a third electrically conductive pad attached to a top of a second interconnectable circuit board, (d) cut marks indicating safe locations for separating the circuit board, and (e) a second cut mark adjacent to the first cut mark where the area between the first and second cut mark can be utilized to make a safe cut through the circuit board.

The present invention relates generally to electric circuit testing, building, or implementing using a breadboard-style printed circuit board (PCB). Aspects of the present invention include eliminating the need to use hookup wires when building and testing electric circuits on PCBs. In one or more embodiments, a PCB system having rows and columns of signal tie points connected in a breadboard layout and using an embedded wire and a solder bridge to form partial connections between signal tie points may be built. In one or more embodiments, an embedded wire and solder bridge is capable of connecting a column of signal tie points, and/or an embedded wire and solder bridge is capable of connecting a power rail to a signal tie point. Thus, a circuit may be implemented and tested by applying a small amount of solder to the solder bridge without the need for hookup wire.

The description relates to prototyping systems, including hubs for electrically connecting devices. One example can include an electrically insulative substrate and at least two connector tabs defined by the substrate, each connector tab including a data contact, a power contact, and a ground contact positioned over the substrate. A data bus can be positioned relative to the substrate and electrically connect all of the data contacts, a power bus can be positioned relative to the substrate and electrically connect all of the power contacts, and a ground bus can be positioned relative to the substrate and electrically connect all of the ground contacts.

A method includes identifying a first output terminal of a radio frequency front end (RFFE) switch including a single pole input terminal and a number (N) of output terminals, the first output terminal selectively connected to a single RF band path. Each of the N output terminals is a component of a respective one of N throws of the RFFE switch, with N being greater than one. The N output terminals include the first output terminal corresponding to a first throw of the N throws and at least one additional output terminal not connected to any radio frequency (RF) band path. The at least one additional output terminal includes a second output terminal corresponding to a second throw of the N throws. The method includes forming a parallel connection between the single pole input terminal and the single RF band path. The parallel connection provides at least two parallel branches for routing RF signals being transceived between the single pole input terminal and the single RF band path.

A method includes identifying a first output terminal of a radio frequency front end (RFFE) switch including a single pole input terminal and a number (N) of output terminals, the first output terminal selectively connected to a single RF band path. Each of the N output terminals is a component of a respective one of N throws of the RFFE switch, with N being greater than one. The N output terminals include the first output terminal corresponding to a first throw of the N throws and at least one additional output terminal not connected to any radio frequency (RF) band path. The at least one additional output terminal includes a second output terminal corresponding to a second throw of the N throws. The method includes forming a parallel connection between the single pole input terminal and the single RF band path. The parallel connection provides at least two parallel branches for routing RF signals being transceived between the single pole input terminal and the single RF band path.