The invention discloses a circuit board enhancing structure and a manufacture method thereof. The method includes the following steps: providing a substrate; forming a first circuit on the substrate; forming a first dielectric layer enclosing the first circuit on the substrate; forming a first opening on the first dielectric layer; forming a first pattern photoresist layer on the first dielectric layer to divide a surface of the first dielectric layer as a first structure enhancing area and a second circuit area, wherein the first opening is disposed in the first structure enhancing area; forming a second circuit in the second circuit area and a first enhancing structure in the first opening, wherein the first enhancing structure protrudes from the first opening; removing the first pattern photoresist layer; and forming a second dielectric layer enclosing the second circuit and the first enhancing structure on the first dielectric layer.

A quantum phased array comprising one or more arrays of emitter elements each emitting one or more particles having one or more quantum wavefunctions; one or more a phase shifting elements coupled to the emitter elements, each of the phase shifting elements comprising a source of a vector potential applying one or more phase shifts to the one or more quantum wavefunctions; and a control circuit coupled to the one or more phase shifting elements, the control circuit configuring the one or more vector potentials to control an interference of the quantum wavefunctions forming a distribution of the one or more particles at a target, and wherein the distribution is described by a wavefunction interference pattern resulting from the interference controlled by the vector potentials.

A printed circuit board, in which two or more copper clad laminates (CCLs) are laminated vertically from an uppermost circuit layer to a lowermost circuit layer, includes a non-destructive testing area, mislamination identifying portions in the non-destructive testing area, the mislamination identifying portions being in the CCLs, respectively, through-via holes vertically exposing the mislamination identifying portions, respectively, in the non-destructive testing area, the through-via holes being spaced apart from each other by a first interval, and a probe via extending vertically and being in contact with an end portion of each of the mislamination identifying portions on a same side. A length of the mislamination identifying portion in an N-th (N is an integer of 1 to K) layer CCL in a horizontal direction is longer than a length of the mislamination identifying positioned in an (N-1)-th layer CCL in the horizontal direction.

A generator control unit (GCU) having thermal control includes a GCU housing having a first side and a second side. A printed wiring board (PWB) is within the GCU housing between the first side and the second side. The PWB includes a component side that faces a first side of the GCU housing. At least one through via is positioned through a thickness of the PWB. At least one boss is positioned on the component side of the PWB. The at least one boss extends from a component of the PWB to the first side of the GCU housing.

A flexible circuit board comprises a substrate on which a chip mounting area is defined, a circuit pattern disposed on the substrate, and a protective layer on the circuit pattern, and the circuit pattern includes a plurality of first circuit patterns, a plurality of second circuit patterns, and a plurality of dummy patterns, and the first circuit pattern includes a first pad part, a second pad part, and a first wiring part connected to the first pad part and the second pad part, and the second circuit pattern includes a third pad part, a fourth pad part, and a second wiring part connected to the third pad part and the fourth pad part, and a through hole is disposed in an inner region of the first circuit pattern.

A connection structure is provided. The connection structure includes a first conductive pad, a first insulating layer, a second conductive pad, a second insulating layer, and a third conductive pad. The first insulating layer is disposed on the first conductive pad and includes a first through-hole. The second conductive pad is disposed on the first insulating layer and electrically connected to the first conductive pad through the first through-hole. The second insulating layer is disposed on the second conductive pad and includes a second through-hole and a first recessed portion. The first recessed portion overlaps the first through-hole. The third conductive pad is disposed on the second insulating layer and electrically connected to the second conductive pad through the second through-hole. The third conductive pad extends on a surface of the first recessed portion.

An electronic power device including transistors formed on a circuit assembly formed of a plurality of layers. The layers include gate drive layers, gate return layers, and power layers. A gate drive circuit is formed on the circuit assembly, and is connected to the gate and source of each of the transistors through the gate drive layers and the gate return layers. A voltage supply connection is provided to each of the plurality of transistors interleaved through the power layers. The circuit assembly includes a multilayer circuit board and/or a multilayer ceramic substrate. The ceramic substrate includes the power layers and transistors. The gate drive and return layers and gate drive circuit may be formed within the ceramic substrate or the circuit board. The ceramic substrate may be located in a modular housing. The circuit board may be outside the modular housing or inside the modular housing.

A printed circuit board includes: a first layer including a first ground including a first opening, wherein a first ground wire is within the first opening; a second layer disposed in a direction from the first layer and including a second ground including a second opening, wherein the second opening at least partially overlaps with the first opening and wherein a second ground wire is within the second opening; a third layer between the first layer and the second layer and including a third opening, wherein the third opening at least partially overlaps with the first opening and wherein a first via pad is within the third opening; and a fourth layer between the second layer and the third layer and including a fourth opening, wherein the fourth opening at least partially overlaps with the third opening and wherein a second via pad is within the fourth opening.

A backplane connector includes a housing and a number of terminal modules. Each terminal module includes a number of conductive terminals, a metal shield surrounding member, a first metal shield and a second metal shield. The conductive terminal includes a mating portion and a tail portion. The conductive terminals include a first signal terminal and a second signal terminal. The metal shield surrounding member surrounds the mating portions of the first signal terminal and the second signal terminal. The first metal shield and the second metal shield are in contact with the metal shield surrounding member. As a result, the shielding area is increased and the shielding effect is improved.

A circuit board includes a first layer, a second layer, a third layer, a plurality of plating through holes, at least one first intermediate layer and at least one second intermediate layer. The first layer and the second layer are used as reference voltage planes. A plurality of transmission wires are disposed on the third layer. The transmission wires are coupled to a wireless signal transceiver and a plurality of antenna arrays; wherein the third layer is disposed between the first layer and the second layer. The plating through holes are disposed at sides of the third layer, wherein the plurality of plating through holes are configured to connect the first reference voltage plane with the second reference voltage plane. The first intermediate layer is disposed between the first layer and the third layer, and the second intermediate layer is disposed between the second layer and the third layer.