A circuit board according to an embodiment includes an insulating portion; and a pattern portion disposed on the insulating portion, wherein the insulating portion includes: a first insulating region, and a second insulating region disposed outside the first insulating region and spaced apart from the first insulating region with a separation region therebetween; wherein the pattern portion includes: a first pattern portion for signal transmission; and a second pattern portion including a dummy pattern separated from the first pattern portion, wherein the first pattern portion includes: a first terminal portion disposed on the first insulating region; a second terminal portion disposed on the second insulating region; and a connection portion disposed on the separation region and connecting between the first terminal portion and the second terminal portion, wherein the second pattern portion includes: a second-first pattern portion disposed on the first insulating region; and a second-second pattern portion disposed on the second insulating region and separated from the second-first pattern portion.

Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.

Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer having a first surface and an opposing second surface, wherein the first layer includes an insulating material, wherein the PIC has an active side, an opposing backside, and a lateral side substantially perpendicular to the active side and backside, and wherein the PIC is embedded in the insulating material with the active side facing up; an integrated circuit (IC) in a second layer at the second surface of the first layer, wherein the IC is electrically coupled to the active side of the PIC; and an optical component, having a reflector, optically coupled to the lateral side of the PIC and extending at least partially through the insulating material in the first layer along the lateral side of the PIC.

A circuit board (100) has a first surface (102). A semiconductor chip (200) (first semiconductor chip) is located at the first surface side (102) of the circuit board (100). An insulating layer (300) covers the first surface (102) of the circuit board (100) and the semiconductor chip (200). A conductive path (310) (first conductive path) is electrically connected to the semiconductor chip (200) and extends in the insulating layer (300). A waveguide (320) is optically coupled to the semiconductor chip (200) and extends in the insulating layer (300).

A surface mount transmission line capacitor can have excellent high frequency performance characteristics. The surface mount transmission line capacitor can include a monolithic substrate having a surface, a first electrode formed over the surface, a second electrode arranged over the first electrode, a dielectric layer arranged between the first electrode and second electrode, a first terminal layer exposed along the surface of the substrate and electrically connected with the first electrode, and a second terminal layer exposed along the surface of the substrate and electrically connected with the second electrode. The first terminal layer and the second terminal layer can be contained within a perimeter of the surface of the monolithic substrate.

An all-directions embedded module includes a substrate layer, many first embedded pads, many second embedded pads, and many side wall circuits. The substrate layer comprises a first surface, a second surface opposite to the first surface, and a plurality of side surfaces connected to the first surface and the second surface. The first embedded pads is formed on the first surface. The second embedded pads is formed on the second surface. The side wall circuits embedded in the substrate layer and exposed from the side surfaces. The all-directions embedded module further includes a plurality of first connecting circuits formed on the first surface and a plurality of second connecting circuits formed on the second surface. The first embedded pads is connected to the side wall circuits by the first connecting circuits. The second embedded pads is connected to the side wall circuits by the second connecting circuits.

A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

A substrate with an antenna according to the present disclosure includes a circuit board having one main surface and the other main surface, and an antenna element mounted on the one main surface of the circuit board. When viewed from a thickness direction, an area of the one main surface of the circuit board is larger than an area of the other main surface, and the antenna element is mounted on at least a part of a region that is on the one main surface of the circuit board and that protrudes from the other main surface.

An electronic component manufacturing method includes a blotting process of bringing a conductive paste applied to an end portion of each electronic component body held by a jig into contact with a surface of a surface plate. The blotting process includes simultaneous performance of a distance changing process of changing the distance between an end face of each electronic component body and the surface of the surface plate and a position changing process of changing a two-dimensional position where the end face of the electronic component body is projected on the surface of the surface plate in such a manner that the direction of the movement of two-dimensional position in parallel to the surface of the surface plate successively varies (e.g., along a circular path).