Isolators for high frequency signals transmitted between two circuits configured to operate at different voltage domains are provided. The isolators may include resonators capable of operating at high frequencies with high bandwidth, high transfer efficiency, high isolation rating, and a small substrate footprint. In some embodiments, the isolators may operate at a frequency not less than 30 GHz, not less than 60 GHz, or between 20 GHz and 200 GHz, including any value or range of values within such range. The isolators may include isolator components galvanically isolated from and capacitively coupled to each other. The sizes and shapes of the isolator components may be configured to control the values of equivalent inductances and capacitances of the isolators to facilitate resonance in operation. The isolators are compatible to different fabrication processes including, for example, micro-fabrication and PCB manufacture processes.

An embedded power module includes a substrate, first and second semiconducting dies, first and second gates, and first and second vias. The first semiconducting die is embedded in the substrate and spaced between opposite first and second surfaces of the substrate. The second semiconducting die is embedded in the substrate, is spaced between the first and second surfaces, and is spaced from the first semiconducting die. The first gate is located on the first surface. The second gate is located on the second surface. The first via is electrically engaged to the first gate and the second semiconducting die, and the second via is electrically engaged to the second gate and the first semiconducting die.

A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a laminate inlay embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the laminate inlay and configured to distribute a load current switched by the laminate inlay. A fourth metal layer is positioned between the second metal layer and the laminate inlay and configured as a primary thermal conduction path for heat generated by the laminate inlay during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.

A high voltage semiconductor package includes a semiconductor device. The semiconductor device includes a high voltage semiconductor transistor chip having a front side and a backside. A low voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. A high voltage load electrode is disposed on the backside of the semiconductor transistor chip. The semiconductor package further includes a dielectric inorganic substrate. The dielectric inorganic substrate includes a pattern of first metal structures running through the dielectric inorganic substrate and connected to the low voltage load electrode, and at least one second metal structure running through the dielectric inorganic substrate and connected to the control electrode. The front side of the semiconductor transistor chip is attached to the dielectric inorganic substrate by a wafer bond connection, and the dielectric inorganic substrate has a thickness of at least 50 μm.

An electronic component housing package includes an insulating substrate including a first surface with a mounting region mounting an electronic component, a second surface located opposite to the first surface, a plurality of side surfaces located between the first surface and the second surface, and a corner portion located between two of the side surfaces; an external connection conductor located on the second surface; and a corner conductor connected to the external connection conductor. The corner conductor is located from the external connection conductor toward the corner portion in a manner to increase the distance from the second surface.

A method for contacting and rewiring an electronic component embedded in a PCB in the following manner is disclosed. A first permanent resist layer is applied to one contact side of the PCB. The first permanent resist layer is structured to produce exposures in the area of contacts of the electronic component. A second permanent resist layer is applied onto the structured first permanent resist layer. The second permanent resist layer is structured to expose the exposures in the area of the contacts and to produce exposures in line with the desired conductor tracks. The exposures are chemically coated with copper the copper is electric-plated to the exposures. Excess copper in the areas between the exposures is removed.

A component carrier including a stack with a plurality of electrically insulating layer structures and/or a plurality of electrically conductive layer structures, and a component embedded in the stack, wherein at least a portion of a side wall of the component is exposed.

Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a core layer disposed between a first dielectric layer and a second dielectric layer, a die disposed in a cavity of the core layer, and an encapsulant disposed in the cavity between the die and a sidewall of the cavity. The package further includes a first patterned conductive layer disposed within the first dielectric layer, a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is between the device and the core layer, a second patterned conductive layer disposed within the second dielectric layer, and a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is between the conductive pad and the core layer.

A method of manufacturing component carriers is disclosed. The method includes providing a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, forming a first hole in a core of the stack and subsequently embedding a first component in the first hole, thereafter forming a second hole in the same core of the stack and subsequently embedding a second component in the second hole. A component carrier has a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure. A first hole is formed in a core of the stack. A first component is embedded in the first hole. A second hole is formed in the same core of the stack and subsequently a second component is embedded in the second hole.

This application provides an embedded substrate, a circuit board assembly, and an electronic device. The embedded substrate in this application includes an insulation layer, and an electronic element and a conductive connector that are embedded inside the insulation layer. The conductive connector is electrically connected to the electronic element. The conductive connector includes at least one fuse unit, the fuse unit includes a fusible structure and two electrical connection ends, the fusible structure is connected between the two electrical connection ends in a direction of an electrical path of the conductive connector, and the fusible structure is configured to be blown when a passing current exceeds a preset current threshold, to disconnect an electrical connection between the electronic element and an external connection end. In this application, maintenance and replacement costs are low during current burning prevention, and a volume is compact.