A high frequency amplifier includes an asymmetric Doherty amplifier configured to amplify a high frequency signal having a wavelength A, the high frequency signal being input, and the asymmetric Doherty amplifier including a carrier amplifier and a peak amplifier, the peak amplifier being configured to start an amplifying operation when an output of the carrier amplifier reaches a saturation region and having a saturation output different from a saturation output of the carrier amplifier, a driver amplifier configured to drive the asymmetric Doherty amplifier, a branch circuit configured to branch the high frequency signal amplified by the driver amplifier into an input path on a peak amplifier side and an input path on a carrier amplifier side, a phase adjustment circuit configured to delay either a phase of a signal input to the peak amplifier or a phase of a signal input to the carrier amplifier, the phase adjustment circuit being provided on either the input path on the peak amplifier side or the input path on the carrier amplifier, a first substrate on which the carrier amplifier and the peak amplifier are mounted, and a second substrate on which the driver amplifier, the branch circuit, and the phase adjustment circuit are mounted. An input terminal of the driver amplifier and an input terminal of the carrier amplifier are disposed at positions where the input terminal of the driver amplifier and the input terminal of the carrier amplifier project to each other when the second substrate is stacked on the first substrate. An electrical length from the input terminal of the driver amplifier to an output terminal of the carrier amplifier is set to a phase of (2n+1)×π, where n is an integer greater than or equal to 0.

A circuit board with improved heat dissipation function and a method for manufacturing the circuit board are provided. The circuit board includes a heat dissipation substrate, an insulating layer on the heat dissipation substrate, an electronic component, a base layer on the insulating layer, and a circuit layer on the base layer. The heat dissipation substrate includes a phase change structure and a heat conductive layer wrapping the phase change structure. The heat dissipation substrate defines a first through hole. The insulating layer defines a groove for receiving the electronic component. A second through hole is defined in the circuit layer, the base layer, and the insulating layer. A bottom of the second through hole corresponds to the heat conductive layer. A heat conductive portion is disposed in the second through hole.

An electronic device is disclosed. In one example, the electronic device comprises a carrier board, a metal inlay having a cavity and being arranged in the carrier board. At least one electronic component is arranged at least partially in the cavity and embedded in the carrier board. Electric contacts are located at a castellated edge of the carrier board.

A fiber-composite part having one or more electronic components that are located in arbitrary regions of the internal volume of the part are fabricated using a preform charge. The preform charge has a structure that corresponds to that of the mold cavity in which the part is being formed. By incorporating the electronic components in the preform charge, such components are then precisely located, spatially oriented, and constrained, and such location and orientation is maintained during molding to produce a part with the electronic components in the desired locations and orientations within its internal volume.

An electronic component of the present disclosure includes a first insulating layer that includes impurities, a thin film resistor formed on the first insulating layer, and a barrier layer that is formed in at least one part of a region between the thin film resistor and the first insulating layer and that obstructs transmission of the impurities. The first insulating layer includes a first surface and a concave portion that is hollowed with respect to the first surface, and the barrier layer may include a first part embedded in the concave portion and a second part formed along the first surface of the first insulating layer from an upper area of the first part.

A semiconductor device package includes a carrier and an encapsulant disposed on the carrier. At least one portion of the encapsulant is spaced from the carrier by a space.

An example electronic device includes a housing, a first board and a second board disposed in an interior of the housing and disposed to face each other in a first direction, an interposer extending to surround an interior space between the first board and the second board, a first conductive layer disposed to face the first board and including a first conductive area, a second conductive layer disposed to face the second board and including a second conductive area, an insulation layer disposed between the first conductive layer and the second conductive layer, a first insulation part disposed between the first conductive layer and the first board and covering the first conductive area, a second insulation part disposed between the second conductive layer and the second board and covering the second conductive area, a first plating area extending from the first conductive layer to the second conductive layer, on a first side surface of the insulation layer, and a second plating area extending from the first conductive layer to the second conductive layer, on a second side surface of the insulation layer.

A multi-device graded embedding package substrate includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer includes a first conductive copper pillar layer and a first device cavity. The second dielectric layer includes a first wiring layer located in a lower surface of the second dielectric layer, a second conductive copper pillar layer and a heat dissipation copper block layer provided on the first wiring layer. The third dielectric layer includes a second wiring layer, a third conductive copper pillar layer provided on the second wiring layer. A first device is attached to the bottom of the first device cavity, and a terminal of the first device is in conductive connection with the second wiring layer. A second device is attached to the bottom of a second device cavity penetrating through the first, second and third dielectric layers.

A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor die, and a first capacitor. The substrate has a wiring structure. The redistribution layer is disposed over the substrate. The first semiconductor die is disposed over the redistribution layer. The first capacitor is disposed in the substrate and is electrically coupled to the first semiconductor die. The first capacitor includes a first capacitor substrate, a plurality of first capacitor cells, and a first through via. The first capacitor substrate has a first top surface and a first bottom surface. The first capacitor cells are disposed in the first capacitor substrate. The first through via is disposed in the first capacitor substrate and electrically couples the first capacitor cells to the wiring structure on the first top surface and the first bottom surface.

A case which is configured of a cover comprising an electronic device, and which is characterized in that the electronic device is inserted into the cover. A case which is configured of a cover comprising an electronic device, and which has an improved storage capacity, while maintaining the stiffness required for a case.