Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimagable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.

The present disclosure relates to a method for manufacturing a circuit board. The method for manufacturing the circuit board includes forming a patterned first dielectric layer on a substrate; forming an adhesive layer on the patterned first dielectric layer; forming a second dielectric layer on the adhesive layer; and patterning the second dielectric layer and the adhesive layer.

A three-dimensional wiring board production method is provided that includes: a preparation step of preparing a resin film (1) having a breaking elongation of 50% or more; a first metal film formation step of forming a first metal film (3) on a surface of the resin film; a pattern formation step of performing patterning on the first metal film to form a desired pattern; a three-dimensional molding step of performing three-dimensional molding by heating and pressurizing the resin film; and a second metal film formation step of forming a second metal film (21) on the first metal film having a pattern formed thereon. In the first metal film formation step, metal is deposited in a particle state to form the first metal film in a porous state.

A photosensitive insulating paste according to preferred embodiments of the present disclosure contains glass frit, a first inorganic filler, a second inorganic filler, an alkali-soluble polymer, a photosensitive monomer, a photopolymerization initiator, and a solvent. The first inorganic filler has a refractive index of 1.7 or higher. The second inorganic filler has a refractive index of 1.55 or lower. An electronic component according to preferred embodiments of the present disclosure is produced by using the photosensitive insulating paste.

The present invention relates to methods and systems for deposition of metal conductors using asymmetrical electrolytic plating, in which one surface (e.g., top) of a substrate is coated with an electrical conductor, and an opposite (e.g., bottom, or other) surface of which is not coated. A channel is formed between the two sides of the substrate, passing through the substrate and, in some embodiments, passing through the conductor. Electrolytic plating is performed such that metal is deposited from the edge of the conduct proximal to the channel, along the side walls of the channel, and up to, and in some embodiments on to, the other side of the substrate. Use of etching or plate resist layers are also contemplated.

A multilayer board includes a flexible base material including laminated insulator layers and curved along an X-axis direction on a plane orthogonal or substantially orthogonal to a lamination direction, an interlayer connection conductor on the flexible base material, and a notch pair on the flexible base material at positions symmetrical or substantially symmetrical in the X-axis direction with respect to a position of the interlayer connection conductor, the notch pair extending in a Y-axis direction orthogonal or substantially orthogonal to the X-axis direction on the plane. The interlayer connection conductor is within a region defined by the notch pair and lines respectively joining ends of the notch pair in the Y-axis direction. A radius of curvature of a region of the flexible base material between the notch pair in the X-axis direction being greater than curvature radii of regions outside of the notch pair.

A manufacturing method of a circuit board and a stamp are provided. The method includes the following steps. A circuit pattern and a dielectric layer covering the circuit pattern are formed on a dielectric substrate. A conductive via connected to the circuit pattern is formed in the dielectric layer. A photoresist material layer is formed on the dielectric layer. An imprinting process is performed on the photoresist material layer using a stamp to form a patterned photoresist layer, wherein the pressing side of the stamp facing the circuit pattern becomes sticky when subjected to pressure so as to catch photoresist residue from the photoresist material layer in the imprinting process. A patterned metal layer is formed on a region exposed by the patterned photoresist layer. The patterned photoresist layer is removed.

A method of fabrication and device made by preparing a photosensitive glass substrate comprising at least silica, lithium oxide, aluminum oxide, and cerium oxide, masking a design layout comprising one or more holes to form one or more electrical conduction paths on the photosensitive glass substrate, exposing at least one portion of the photosensitive glass substrate to an activating energy source, exposing the photosensitive glass substrate to a heating phase of at least ten minutes above its glass transition temperature, cooling the photosensitive glass substrate to transform at least part of the exposed glass to a crystalline material to form a glass-crystalline substrate and etching the glass-crystalline substrate with an etchant solution to form one or more angled channels that are then coated.

In fabricating a wiring structure, a first wiring is formed on a substrate. First and second light sensitive insulation layers that are reactive to light of first and second wavelength ranges, respectively, are sequentially formed on the first wiring. First and second exposing processes are performed using the light of the first and second wavelength ranges, respectively, to form first and second exposed portions in the first and second light sensitive insulation layers, respectively. The first and second exposed portions are removed by a developing process to form a hole and an opening, respectively. The hole and the opening extend through the first and second light sensitive insulation layers, respectively, to be connected to one another. A conductive layer is formed in the hole and in the opening, and is planarized to form a first via and a second wiring in the hole and in the opening, respectively.

A method for manufacturing a circuit board includes forming a patterned first dielectric layer on a substrate; forming a first adhesive layer on the patterned first dielectric layer; forming a second dielectric layer on the first adhesive layer; patterning the second dielectric layer to expose a portion of a top surface of the first adhesive layer opposite to the substrate; and filling at least the patterned second dielectric layer with a conductive material, such that the conductive material is in contact with the top surface of the first adhesive layer.