Patent classifications
H05K3/0041
METHOD FOR MANUFACTURING CIRCUIT BOARD AND STACKED STRUCTURE
A method for manufacturing a circuit board includes providing a composite material film including a metal film and a polymeric film, disposing a dielectric layer on the polymeric film to form a stacked structure, forming a circuit layer with a contact pad on a substrate, bonding the stacked structure onto the substrate and the circuit layer, and forming a first opening extending through the metal film to form a patterned metal film. The dielectric layer directly contacts the substrate and entirely covers the circuit layer. The method further includes plasma etching the dielectric layer with the patterned metal film as a mask to form a second opening in the dielectric layer and expose the contact pad in the second opening, removing the composite material film, and depositing a conductive material in the second opening to form a conductive blind hole electrically connected to the contact pad.
Thermally induced graphene sensing circuitry on intelligent valves, actuators, and pressure sealing applications
Thermally induced graphene sensing circuitry and methods for producing circuits from such thermally induced circuits are presented in conjunction with applications to hydrocarbon exploration and production, and related subterranean activities. The thermally induced graphene circuity advantageously brings electrically interconnections otherwise absent on oilfield service tools, enabling components and tools to become smart.
METHOD FOR MANUFACTUNRING A MULTILAYER CIRCUIT STRUCTURE HAVING EMBEDDED TRACE LAYERS
Provided herein are methods for manufacturing a multilayer circuit structure having embedded circuits and the multilayer circuit structure made thereby. A substrate having at least one existing circuit on the surface is provided, then a dielectric layer is formed to cover the existing circuit. A metal layer is subsequently formed on the dielectric layer. The metal layer is made into a metal hard mask with a pattern by photoimaging, then the pattern is transferred to the dielectric layer underneath by plasma etching to create trenches and pads for vias at the same time. After vias are made on the pads, a conductive metal is deposited into the trenches and vias to form an embedded trace layer in the respective dielectric layer. The excess conductive metal is removed to obtain a new circuit embedded in the dielectric layer and is coplanar with the surface of the dielectric layer.
Coaxial thru-via conductor configurations in electronic packaging substrates
A coaxial thru-via conductor and a method of fabricating the coaxial thru-via conductor can provide enhanced operations for semiconductor devices mounted on a substrate.
COAXIAL THRU-VIA CONDUCTOR CONFIGURATIONS IN ELECTRONIC PACKAGING SUBSTRATES
A coaxial thru-via conductor and a method of fabricating the coaxial thru-via conductor can provide enhanced operations for semiconductor devices mounted on a substrate.
MULTILAYER BOARD AND METHOD FOR MANUFACTURING SAME
Provided are a multilayer board and a method for manufacturing same, in which a different kind of metal layer is formed between an upper metal layer and an interlayer insulating layer, the different kind of metal layer being formed only in a wiring area without being formed in a via area. The multilayer board comprises: a substrate layer; a plurality of first metal layers sequentially stacked on the substrate layer; an interlayer insulating layer formed between two different first metal layers, having a first via hole, and electrically connecting the two different first metal layers through a third metal layer formed in the first via hole; and a second metal layer formed between the upper layer of the two different first metal layers and the interlayer insulating layer.
Component Carrier and Method of Manufacturing the Same
A component carrier includes a stack having a first electrically insulating layer structure and a first electrically conductive layer structure arranged on the first electrically insulating layer structure. The first electrically insulating layer structure has at least one first covered portion, which is covered by the first electrically conductive layer structure, and at least one first non-covered portion, which is not covered by the first electrically conductive layer structure. The first electrically insulating layer structure defines a recess at the at least one first non-covered portion.
THERMALLY INDUCED GRAPHENE SENSING CIRCUITRY ON INTELLIGENT VALVES, ACTUATORS, AND PRESSURE SEALING APPLICATIONS
Thermally induced graphene sensing circuitry and methods for producing circuits from such thermally induced circuits are presented in conjunction with applications to hydrocarbon exploration and production, and related subterranean activities. The thermally induced graphene circuity advantageously brings electrically interconnections otherwise absent on oilfield service tools, enabling components and tools to become smart.
Component Carrier With Embedded Component Exposed by Blind Hole
A method of manufacturing a component carrier is disclosed. The method includes providing a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, embedding a component in the stack, drilling a blind hole in the stack towards the embedded component, and thereafter extending the blind hole by etching to thereby expose a surface portion of the embedded component.
PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD
A printed wiring board includes resin insulating layers including an outermost resin insulating layer, conductor layers laminated on the resin insulating layers, a copper layer formed in the outermost insulating layer, and metal bumps formed on the copper layer such that the bumps have upper surfaces protruding from the outermost insulating layer and that each metal bump includes Ni film, Pd film and Au film. The copper layer is reduced in diameter toward upper surface side such that the copper layer has upper and bottom surfaces and each upper surface has diameter that is smaller than diameter of each bottom surface, the outermost insulating layer has cylindrical sidewalls formed such that at least part of the copper layer is not in contact with the sidewalls, and the bumps are formed such that the Ni film is filling spaces between the copper layer and the sidewalls of the outermost insulating layer.