A method of forming a metallic pattern on a substrate is provided. The method includes applying onto a metallic surface, a chemically surface-activating solution having an activating agent that chemically activates the metallic surface; non-impact printing an etch-resist ink on the activated surface to produce an etch resist mask according to a predetermined pattern, wherein at least one ink component within the etch-resist ink undergoes a chemical reaction with the activated metallic surface to immobilize droplets of the etch-resist ink when hitting the activated surface; performing an etching process to remove unmasked metallic portions that are not covered with the etch resist mask; and removing the etch-resist mask.

A method of making a device patterned with one or more electrically conductive features includes depositing a conductive material layer over an electrically insulating surface of a substrate, depositing an anti-corrosive material layer over the conductive material layer, and depositing an etch-resist material layer over the anti-corrosive material layer. The etch-resist material layer may be deposited over the anti-corrosive material layer, and the anti-corrosive material layer forming a bi-component etch mask in a pattern resulting in covered portions of the conductive material layer and exposed portions of the conductive material layer, the covered portions being positioned at locations corresponding to one or more conductive features of the device. A wet-etch process is performed to remove the exposed portions of the conductive material layer from the electrically insulating substrate, and the bi-component etch mask is removed to expose the remaining conductive material. Systems and devices relate to devices with patterned features.

The present application provides a circuit board and a manufacturing method therefor. The circuit board includes: a core board, at least one chip, a first circuit layer, and a first insulating layer. A groove body is formed on the core board. The chip is provided in the groove body. The chip is provided with a first lead-out terminal. The first circuit layer is provided on at least one side of the core board. The first insulating layer is provided between the core board and the first circuit layer. The first lead-out terminal passes through the first insulating layer and is connected to the first circuit layer, so that the chip is electrically connected to the first circuit layer. Thus, the wiring between the chip and the circuit is more flexible.

A flexible printed circuit board includes: a base film having a hole for forming a through hole; and a coil-shaped wiring layer layered on at least one surface side of the base film, wherein the wiring layer includes a land portion arranged at an inner peripheral surface of the hole and at a peripheral portion of the hole of the base film, and a winding portion arranged in a spiral shape with the land portion as an inside end portion or an outside end portion, wherein the winding portion includes a first winding portion that is an outermost circumference and a second winding portion that is inside relative to the outermost circumference, and wherein a ratio of an average thickness of the land portion to an average thickness of the second winding portion is 1.1 or more and 5 or less.

A wiring board includes core substrate, a first build-up layer on first surface of the substrate and including conductive and insulating resin layers, and a second build-up layer on second surface of the substrate and including conductive and insulating resin layers. The first build-up is formed such that each conductive layer includes a metal foil layer and a plating layer on the foil layer and the foil layer of a conductive layer on an outermost resin layer has thickness greater than thickness of the foil layer of a conductive layer on a non-outermost resin layer, and the second build-up is formed such that each conductive layer includes a metal foil layer and a plating layer on the foil layer and the foil layer of a conductive layer on an outermost resin layer has thickness greater than thickness of the foil layer of a conductive layer on a non-outermost resin layer.

A ceramic substrate is provided in which an inclined protrusion is formed on boundary surface of a metal layer bonded to a ceramic base so as to increase bonding strength; and a manufacturing method therefor. The inclined protrusion may include: a tapered protrusion and a multi-stepped protrusion formed on the boundary surface of the metal layer according to an interval between the metal layer bonded to the ceramic base and a neighboring metal layer, wherein a multi-stepped protrusion having an inclination angle within a predetermined angle range with respect to the ceramic base may be formed on the boundary surface of the metal layer where stress is concentrated, such as the short edge, apex, corner, and the like, and a tapered protrusion may be formed on a remaining portion of the boundary surface of the metal layer.

A ceramic copper circuit board according to an embodiment includes a ceramic substrate and a first copper part. The first copper part is bonded at a first surface of the ceramic substrate via a first brazing material part. The thickness of the first copper part is 0.6 mm or more. The side surface of the first copper part includes a first sloped portion. The width of the first sloped portion is not more than 0.5 times the thickness of the first copper part. The first brazing material part includes a first jutting portion jutting from the end portion of the first sloped portion. The length of the first jutting portion is not less than 0 μm and not more than 200 μm. The contact angle between the first jutting portion and the first sloped portion is 65° or less.

A ceramic copper circuit board according to an embodiment includes a ceramic substrate and a first copper part. The first copper part is bonded at a first surface of the ceramic substrate via a first brazing material part. The thickness of the first copper part is 0.6 mm or more. The side surface of the first copper part includes a first sloped portion. The width of the first sloped portion is not more than 0.5 times the thickness of the first copper part. The first brazing material part includes a first jutting portion jutting from the end portion of the first sloped portion. The length of the first jutting portion is not less than 0 μm and not more than 200 μm. The contact angle between the first jutting portion and the first sloped portion is 65° or less.

A ceramic copper circuit board according to an embodiment includes a ceramic substrate and a first copper part. The first copper part is bonded at a first surface of the ceramic substrate via a first brazing material part. The thickness of the first copper part is 0.6 mm or more. The side surface of the first copper part includes a first sloped portion. The width of the first sloped portion is not more than 0.5 times the thickness of the first copper part. The first brazing material part includes a first jutting portion jutting from the end portion of the first sloped portion. The length of the first jutting portion is not less than 0 μm and not more than 200 μm. The contact angle between the first jutting portion and the first sloped portion is 65° or less.

A method for manufacturing a multilayer wiring substrate includes forming a resist layer having mask pattern, forming a conductor layer having conductor pattern using the resist layer, removing the resist layer, forming an insulating layer on the conductor layer such that the insulating layer is laminated on the conductor layer, forming a subsequent resist layer having mask pattern such that the subsequent resist layer is formed on the insulating layer, and forming a subsequent conductor layer having conductor pattern using the subsequent resist layer. The forming of the resist layer includes conducting first correction in which formation position of entire mask pattern of the resist layer is corrected with respect to reference position, and conducting second correction in which shape of the mask pattern of the resist layer is corrected with respect to reference shape, and the forming of the subsequent resist layer does not include conducting the second correction.