A multi-layer metal core printed circuit board (MCPCB) has mounted on it at least one or more heat-generating LEDs and one or more devices configured to provide current to the one or more LEDs. The one or more devices may include a device that carries a steep slope voltage waveform. Since there is typically a very thin dielectric between the patterned copper layer and the metal substrate, the steep slope voltage waveform may produce a current in the metal substrate due to AC coupling via parasitic capacitance. This AC-coupled current may produce electromagnetic interference (EMI). To reduce the EMI, a local shielding area may be formed between the metal substrate and the device carrying the steep slope voltage waveform. The local shielding area may be conductive and may be electrically connected, to a DC voltage node adjacent to the one or more devices.

A process for thermoforming a circuit onto a three-dimensional part comprises applying electrically conductive lines on a substrate to form a flexible circuit. The flexible circuit is heated to a temperature sufficient to thermoform the substrate into a shape that conforms to said three-dimensional part and attached to the three-dimensional part.

A manufacturing method of a circuit board. The manufacturing method includes: providing a first substrate; forming an opening on the first substrate; disposing a second substrate, which has a plurality of through holes in the opening; forming an adhesive layer between the first substrate and the second substrate; forming a bonding layer on the first substrate and the second substrate; forming a metal layer on the bonding layer; and patterning the metal layer to form a circuit layer. A circuit board is also disclosed in the disclosure.

A wiring board includes a wiring layer, an insulating layer, an oxide thin film, a seed layer, and a conductive layer. The insulating layer is laminated on the wiring layer and includes an opening portion that penetrates until the wiring layer. The oxide thin film is formed on a surface of the insulating layer including an inner wall surface of the opening portion. The seed layer is made of metal and that is laminated on the oxide thin film at a position of the opening portion. The conductive layer is formed on the seed layer. The oxide thin film is a thin film that has a thickness of 1 to 100 angstroms and covers a surface of the insulating layer including the inner wall surface of the opening portion and a surface of the wiring layer exposed from a bottom portion of the opening portion.

The invention includes methods of forming electronic circuitry on a target surface using intense pulsed light-induced mass transfer (IPLMT) of metal nanoparticles (NPs) by applying a pliable mask to a target surface, coating a carrier film with metal NPs, mounting the carrier film to the target surface and over the pliable mask so that the pliable mask is sandwiched between the target surface and the metal NPs. and exposing the metal NPs to light energy to cause atoms of the metal NPs to evaporate and transport through openings of the pliable mask and condense on the target surface, producing a conductive pattern of condensed metal on the target surface. Certain implementations may utilize a kirigami-patterned pliable mask to enhance conformity to a freeform 3D target surface. In certain implementations, zinc (Zn) may be formed by IPLMT of Zn NPs to the target surface.

A method of patterning holes includes placing a substrate on a stage of a laser system, the substrate having a graphene layer on a surface thereof, generating a pulse laser from the laser system, and forming a plurality of hole patterns spaced apart from each other on the graphene layer by irradiating the pulse laser while the graphene layer is in motion.

A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.

A method for making a circuit board comprising: providing a silver clad laminate comprising a substrate and two silver foils; forming at least one through hole on the silver clad laminate, the through hole comprises an annular middle wall and two annular edge walls connected to two sides of the annular middle wall; forming an organic conductive film on the annular middle wall; forming a dry film pattern layer on the second area; plating copper to form a copper circuit layer on the first area, and to form a via hole in the through hole; removing the dry film pattern layer; and etching the second area of the silver foil away. The first area changes to a silver circuit layer. The copper circuit layer and the silver circuit layer define a conductive circuit layer. A circuit board made by the method is also provided.

A method for making a circuit board comprising: providing a silver clad laminate comprising a substrate and two silver foils; forming at least one through hole on the silver clad laminate, the through hole comprises an annular middle wall and two annular edge walls connected to two sides of the annular middle wall; forming an organic conductive film on the annular middle wall; forming a dry film pattern layer on the second area; plating copper to form a copper circuit layer on the first area, and to form a via hole in the through hole; removing the dry film pattern layer; and etching the second area of the silver foil away. The first area changes to a silver circuit layer. The copper circuit layer and the silver circuit layer define a conductive circuit layer. A circuit board made by the method is also provided.

An electronic device having a substrate with a metal structure, a mono-layer coating of a selected silane composition on a surface of the metal structure, and an organic layer on the mono-layer coating, wherein the mono-layer coating improves the interfacial adhesion strength between the metal surface and the organic material.