Multilayer articles that include electrical circuits are prepared by the adhesive transfer of electrical circuit elements to the surface of an adhesive. A number of different methodologies are used, with all of the methodologies including the use of simple layers of circuit-forming material on a releasing substrate and structuring to generate circuit elements which can be transferred to an adhesive surface. In some methodologies, a structured releasing substrate is used to selectively transfer circuit-forming material, either from protrusions on the releasing substrate or from depressions on the releasing substrate. In other methodologies, an unstructured releasing substrate is used and either embossed to form a structured releasing substrate or contacted with a structured adhesive layer to selectively transfer circuit-forming material.

An item may include fabric or other materials formed from intertwined strands of material. The item may include circuitry that produces signals. The strands of material may include non-conductive strands and conductive strands. The conductive strands may carry the signals produced by the circuitry. Each conductive strand may have a strand core, a conductive coating on the strand core, and an insulating layer on the conductive coating. The strand cores may be strands formed from polymer. The conductive coating may be formed from metal. Electrical connections may be made between intertwined conductive strands by selectively removing portions of the outer insulating layer to expose the conductive cores of overlapping conductive strands. A conductive material such as solder or conductive epoxy may be applied to the exposed portions of the conductive cores to electrically and mechanically connect the overlapping conductive strands.

Systems and methods for producing electromagnetic devices are provided. The systems and methods allow for an electromagnetic device having both a substrate (e.g., polymer) and conductive material (e.g., metal) to be manufactured without using masks or other outside objects disposed over a surface (e.g., the substrate) onto which the conductive material is deposited. In one exemplary embodiment, the method includes performing additive manufacturing using a polymer to produce a device having a plurality of interconnected walls and a plurality of frequency selective surface elements, and then coating portions of the device with a conductive material. A plurality of shadowing features are formed as part of one or more of the walls to protect the frequency selective surface elements from being coated by the conductive material. Other methods, and a variety of systems that can result from the disclosed methods, are also provided.

A component carrier with a double layer structure is illustrated and described. The double layer structure includes an electrically conductive patterned layer structure and a further patterned layer structure made of a two-dimensional material. The patterned layer structure and the further patterned layer structure have at least partly the same pattern. In an embodiment the component carrier includes a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure and at least one double layer structure connected with the stack.

A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.

A circuit board comprising a substrate and a circuit trace. The substrate includes a surface etched via ion milling over a circuit area such that the surface has an increased roughness. The circuit trace forms portions of an electronic circuit and may be created from a thin conductive film deposited on the surface within the circuit area. The circuit trace adheres more strongly to the roughened substrate surface, which prevents the circuit trace from peeling or becoming delaminated from the substrate surface.

A glass wiring substrate includes a glass substrate, a first wiring portion being formed on a first surface of the glass substrate, a second wiring portion being formed on a second surface opposite to the first surface; a through-hole formed in a region of the glass substrate in which the first wiring portion and the second wiring portion are not formed, the through-hole having a diameter on a second surface side larger than a diameter on a first surface side; and a through-hole portion formed in the through-hole, one end portion of the through-hole portion extending to the first wiring portion, the other end portion of the through-hole portion extending to the second wiring portion, in which a wiring pitch P1 of the first wiring portion in the vicinity of the through-hole portion is narrower than a wiring pitch P2 of the second wiring portion in the vicinity of the through-hole portion.

A structure, a semiconductor device and a manufacturing method thereof are provided. The structure includes a core layer and a build-up stack disposed on the core layer. The core layer includes a first core dielectric layer, a second core dielectric layer, through vias, and a patterned conductive plate. The second core dielectric layer is disposed on the first core dielectric layer. The through vias cross the first core dielectric layer and the second core dielectric layer. The patterned conductive plate is disposed on the first core dielectric layer and is electrically insulated from the through vias. The build-up stack includes interconnected conductive patterns electrically connected to the through vias. A bottom surface of the patterned conductive plate is coplanar with an interface of the first core dielectric layer and the second core dielectric layer.

A structure, a semiconductor device and a manufacturing method thereof are provided. The structure includes a core layer and a build-up stack disposed on the core layer. The core layer includes a first core dielectric layer, a second core dielectric layer, through vias, and a patterned conductive plate. The second core dielectric layer is disposed on the first core dielectric layer. The through vias cross the first core dielectric layer and the second core dielectric layer. The patterned conductive plate is disposed on the first core dielectric layer and is electrically insulated from the through vias. The build-up stack includes interconnected conductive patterns electrically connected to the through vias. A bottom surface of the patterned conductive plate is coplanar with an interface of the first core dielectric layer and the second core dielectric layer.

The present disclosure provides a composite conductive substrate exhibiting enhanced properties both in the folding endurance and the electric conductivity and a method of manufacturing the composite conductive substrate. A composite conductive substrate according to an exemplary embodiment of the present disclosure includes: an insulating layer; a metal nanowire structure embedded beneath one surface of the insulating layer; and a metal thin film coupled to the metal nanowire structure. The composite conductive substrate may be fabricated in an order of the insulating film, the metal nanowire structure, and the metal thin film, or vice versa.