A glass circuit board includes, on a glass substrate, a stress relief layer, a seed layer, and an electroplated layer including copper plating. The stress relief layer is an insulator formed by dry coating method and applies a compressive residual stress to the glass substrate at room temperature. The stress relief layer thus reduces cracking, fracturing or warpage of the glass substrate caused by thermal expansion and shrinkage of the copper plating due to heating and cooling of the glass circuit board during manufacturing or thermal cycling, ensuring high connection reliability of the glass circuit board.

Depicted embodiments are directed to an Application Specific Electronics Packaging (“ASEP”) system, which enables the manufacture of additional products using reel to reel (68a, 68b) manufacturing processes as opposed to the “batch” processes used to currently manufacture electronic products and MIDs. Through certain ASEP embodiments, it is possible to integrate connectors, sensors, LEDs, thermal management, antennas, RFID devices, microprocessors, memory, impedance control, and multi-layer functionality directly into a product.

A method of making an electrical component includes transmitting electrical energy from a power source through one or more deposition anodes, through an electrolyte solution, and to an intralayer electrical-connection feature of a build plate, such that material is electrochemically deposited onto the intralayer electrical-connection feature and forms an interlayer electrical-connection feature. The method also includes securing a dielectric material so that the dielectric material contacts and electrically insulates the intralayer electrical-connection feature and contacts and at least partially electrically insulates the interlayer electrical-connection feature. The method additionally includes depositing a seed layer onto the dielectric material and the interlayer electrical-connection feature, electrochemically depositing material onto the seed layer, to form at least one second intralayer electrical-connection feature of the electrical component, and removing any one or more portions of the seed layer onto which no portion of the at least one second intralayer electrical-connection feature is formed.

The present invention includes a method of fabricating an integrated RF power condition capacitor with a capacitance greater than or equal to 1 nf and less than 1 mm.sup.2, and a device made by the method.

An electroplating apparatus includes an anode and a cathode, a power supply, a regulating plate, and a controller. The power supply is electrically connected to the anode and the cathode. The regulating plate is disposed between the anode and the cathode. The regulating plate includes an insulation grid plate and a plurality of wires. The controller is electrically connected to the plurality of wires to control a state of an electromagnetic field around the plurality of wires. An electroplating method is also provided.

A wiring board (10) includes a substrate (11) and a mesh wiring layer (20) disposed on the substrate (11) and including a plurality of wiring lines (21, 22). The substrate (11) has a transmittance of 85% or more for light with a wavelength of 400 nm or more and 700 nm or less. The wiring lines (21, 22) have a surface roughness Ra, and the surface roughness Ra is 100 nm or less.

The invention, which relates to the technical field of circuit boards, specifically discloses a method for manufacturing an embedded circuit board, an embedded circuit board, and an application thereof. The method includes: providing a substrate, wherein an electronic component is embedded in the substrate, a pad is arranged on a side surface of the electronic component, and an end surface of the pad is flush with a same side surface of the substrate; forming a metallic layer on a side surface of the substrate adjacent to the pad by sputtering, evaporation, electroplating or chemical vapor deposition; and patterning the metallic layer to obtain a circuit board covered with the metallic layer on the pad, wherein the metallic layer on the pad protrudes beyond the same side surface of the substrate.

A method for forming a metal film includes forming an oxide layer on a to-be-treated surface of a to-be-treated object by bringing the to-be-treated surface into contact with a reaction solution containing fluorine and an oxide precursor, removing fluorine in the oxide layer, supporting a catalyst on the oxide layer by bringing the oxide layer into contact with a catalyst solution, and depositing a metal film on the oxide layer by bringing the oxide layer into contact with an electroless plating liquid.

The present disclosure provides a wiring structure, a preparation method thereof, and a display device. The wiring structure includes a substrate; a pre-arranged layer located on the substrate; and an electrode wiring covering the pre-arranged layer; wherein in the direction perpendicular to an extending direction of the electrode wiring and parallel to a plane on which the substrate is located, an orthographic projection of the pre-arranged layer on the substrate is located within an orthographic projection of the electrode wiring on the substrate, and a side surface of the pre-arranged layer is inclined relative to the plane on which the substrate is located.

The present invention relates to a surface modifier for electrolytic nickel plating including at least one carboxyl group-containing compound and a nickel electroplating solution including the surface modifier. The use of the nickel electroplating solution according to the present invention enables efficient formation of a plated nickel layer with high surface roughness and mattness even without performing strong electrolysis, unlike in the prior art.