Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed.

A printed circuit board includes an insulating layer, a circuit pattern on the insulating layer, and a surface treatment layer on the circuit pattern. The surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern.

A laminated structure and the manufacturing methods thereof are provided. The structure includes an interconnect substrate having a first surface and a second surface opposite to the first surface, an insulating encapsulant laterally wrapping the interconnect substrate, and a redistribution structure disposed on the first surface of the interconnect substrate and electrically connected with the interconnect substrate. The redistribution structure has a third surface facing the first surface and a fourth surface opposite to the third surface. The redistribution structure includes first pads, second pads located beside the first pads, and protective patterns disposed on the first pads and covering the first pads. The first pads include pad portions protruded from the fourth surface and the protective patterns are in contact with sidewalls and top surfaces of the pad portions of the first pads.

A component carrier includes an electrically insulating layer structure with a first main surface and a second main surface, a through hole extends through the electrically insulating layer structure between the first main surface and the second main surface. The through hole has a first tapering portion extending from the first main surface and a second tapering portion extending from the second main surface. The through hole is delimited by a first plating structure on at least part of the sidewalls of the electrically insulating layer structure and a second plating structure formed separately from and arranged on the first plating structure. The second plating structure includes an electrically conductive bridge structure connecting the opposing sidewalls.

A ceramic electronic component that includes an electronic component body having a superficial base ceramic layer; a surface electrode on a surface of the electronic component body, a peripheral section of the surface electrode having an opening therein; and a covering ceramic layer covering the peripheral section of the surface electrode and the opening therein.

Provided is a wiring circuit board that allows the electrical connection between the elements and the terminals to be easy and sure. The wiring circuit board includes an insulating base layer, a plurality of wires with different thicknesses from each other, and an insulating cover layer sequentially toward an upper side. The wires include a first wire having the greatest thickness. The wiring circuit board further includes a plurality of terminals disposed on an upper surface of the insulating base layer. The terminals are electrically connected with the wires, respectively. The upper surfaces and of the terminals are each located at an upper side as compared to an upper surface of the insulating cover layer (a wire covering portion) covering the first wire.

An object of the present invention is to provide an Sn—Bi—Cu—Ni solder alloy or the like which has a low melting point, excellent ductility, and high tensile strength, and in which if soldering is performed on a Cu electrode subjected to electroless Ni plating treatment, a solder joint formed through this soldering exhibits high shear strength. In addition, another object of the present invention is to provide an Sn—Bi—Cu—Ni solder alloy in which a solder joint formed through soldering exhibits high shear strength even for a Cu electrode which has not been subjected to plating treatment. Furthermore, still another object of the present invention is to provide, in addition to the above-described objects, a solder alloy or the like of which yellowish discoloration can be suppressed and in which change in viscosity of a solder paste over time can be suppressed. The solder alloy has an alloy composition consisting of, by mass %, 31% to 59% of Bi, 0.3% to 1.0% of Cu, 0.01% to 0.06% of Ni, 0.0040% to 0.025% of As, and a balance of Sn.

A flexible printed circuit board (FPCB), which is applied to various electronic display devices, may include a base, a first metal layer and a second metal layer on both surfaces of the base, a first plating layer on the first metal layer, a second plating layer on the second metal layer, and a first insulating pattern and a second insulating pattern respectively disposed on some region of the first plating layer and the second plating layer, wherein the first plating layer and the second plating layer may have different thicknesses.

A printed circuit board includes an insulating layer, a circuit pattern embedded in the insulating layer and including a first metal layer, a second metal layer and a third metal layer disposed between the first metal layer and the second metal layer, and a connection conductor disposed on one surface of the insulating layer and connected to the circuit pattern, wherein the first metal layer is exposed through the one surface of the insulating layer.

A printed circuit board module (10) has a printed circuit board (20) with a first side (21), a second side (22) and a contact hole (30). A sleeve-type via (32) is provided in the contact hole 30. An annular ring (35, 36) is associated with the via (32), on at least one side (33, 34). The annular ring (35, 36) is arranged on the first side (21) or on the second side (22) of the printed circuit board (20). The annular ring (35, 36) is electrically connected to the via (32). The annular ring (35, 36) has an annular ring edge (40), at least in sections. The printed circuit board module (10) has a solder resist layer (50). It extends, at least in sections, from outside the annular ring edge (40) over the annular ring edge (40) to an outer region (42) of the annular ring (35, 36). An inner region (44) not covered with the solder resist layer (50), remains on the annular ring (35, 36).