A surface treated copper foil 1 includes a copper foil 2, and a first surface treatment layer 3 formed on one surface of the copper foil 2. The first surface treatment layer 3 of the surface treated copper foil 1 has a Ni concentration of 0.1 to 15.0 atm % based on the total amount of elements of C, N, O, Zn, Cr, Ni, Co, Si, and Cu, in an XPS depth profile obtained by performing sputtering at a sputtering rate of 2.5 nm/min (in terms of SiO.sub.2) for 1 minute. A copper clad laminate 10 includes the surface treated copper foil 1 and an insulating substrate 11 adhered to the first surface treatment layer 3 of the surface treated copper foil 1.

A surface treated copper foil 1 includes a copper foil 2, and a first surface treatment layer 3 formed on one surface of the copper foil 2. The first surface treatment layer 3 of the surface treated copper foil 1 has a Ni deposited amount of 20 to 200 μg/dm.sup.2 and a Zn deposited amount of 20 to 1,000 μg/dm.sup.2. A copper clad laminate 10 includes the surface treated copper foil 1 and an insulating substrate 11 adhered to the first surface treatment layer 3 of the surface treated copper foil 1.

An advanced electrodeposited copper foil having island-shaped microstructures and a copper clad laminate using the same are provided. The advanced electrodeposited copper foil includes a micro-roughened surface. The micro-roughened surface has a plurality of copper crystals, a plurality of copper whiskers and a plurality of copper crystal groups which are in a non-uniform distribution and form into island-shaped patterns.

A surface treated copper foil 1 includes a copper foil 2, and a first surface treatment layer 3 formed on one surface of the copper foil 2. The first surface treatment layer 3 of the surface treated copper foil 1 has a root mean square gradient of roughness curve elements RΔq according to JIS B0601:2013 of 5 to 28°. A copper clad laminate 10 includes the surface treated copper foil 1 and an insulating substrate 11 adhered to the first surface treatment layer 3 of the surface treated copper foil 1.

A circuit board includes a substrate, a plurality of contacts disposed on a surface of the substrate, and a solder mask. The contacts have a plurality of plating regions and a metal layer on the plating regions, and the plating regions have at least two different sizes. The solder mask covers the surface of the substrate and covers edges of the plating regions, in which topmost surfaces of the contacts are below a top surface of the solder mask, and a gap between the topmost surfaces of the contacts and the top surface of the solder mask is larger than 0 μm and is smaller than 5 μm.

A component carrier and a method for manufacturing the same are disclosed. The component carrier includes an electrically conductive layer structure and an overhanging end. A first surface finish is formed on a first surface portion of the electrically conductive layer structure. Furthermore, the component carrier further includes a second surface finish on a second surface portion of the electrically conductive layer structure connected to the first surface finish and extending under the overhanging end.

A surface treated copper foil includes: a copper foil; a finely roughened particle treatment layer of copper on at least one surface of the copper foil, the finely roughened particle treatment layer including fine copper particles having a particle size of 40 to 200 nm; a heat resistance treatment layer containing nickel on the finely roughened particle treatment layer; a rust prevention treatment layer containing at least chromium on the heat resistance treatment layer; and a silane coupling agent treatment layer on the rust prevention treatment layer. An amount of nickel attached in the heat resistance treatment layer is 30 to 60 mg/m2.

Provided are an electrodeposited copper foil, a current collector, an electrode, and a lithium-ion secondary battery comprising the same. The electrodeposited copper foil has a deposited side and a drum side opposite the deposited side. In a first aspect, ΔRS between the deposited side and the drum side is at most about 95 MPa, and the deposited side exhibits a Vv in a range from about 0.15 μm.sup.3/μm.sup.2 to about 1.35 μm.sup.3/μm.sup.2. In a second aspect, the deposited side has a Sku of about 1.5 to about 6.5 and the deposited side exhibits a Vv in a range from about 0.15 μm.sup.3/μm.sup.2 to about 1.35 μm.sup.3/μm.sup.2. The characteristics are beneficial to improve the quality of the electrodeposited copper foil, thereby extending the charge-discharge cycle life of a lithium-ion secondary battery comprising the same.

A method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate, and patterning the conductive layer to define a plurality of plating regions and a plurality of plating lines. The plating regions have at least two different sizes, a first group of the plating regions are interconnected by a first plating line of the plating lines, and a second group of the plating regions are interconnected by a second plating line of the plating lines. A ratio of a total area of the first group of the plating regions to a total area of the second group of the plating regions is from about 1 to about 5. A solder mask is formed on the surface of the substrate to cover the plating lines and partially expose the plating regions. At least one metal layer is electroplated on the exposed plating regions.

A method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate, and patterning the conductive layer to define a plurality of plating regions and a plurality of plating lines. The plating regions have at least two different sizes, a first group of the plating regions are interconnected by a first plating line of the plating lines, and a second group of the plating regions are interconnected by a second plating line of the plating lines. A ratio of a total area of the first group of the plating regions to a total area of the second group of the plating regions is from about 1 to about 5. A solder mask is formed on the surface of the substrate to cover the plating lines and partially expose the plating regions. At least one metal layer is electroplated on the exposed plating regions.