An electrical connection between the backplane and the light-transmissive front electrode of an electrowetting device is provided by forming an aperture through the top front electrode coupled and a substrate coupled thereto and subsequently introducing a flowable, electrically-conductive material into the aperture. The flowable, electrically-conductive material provides an electrical contact between the light-transmissive electrically-conductive layer and the backplane.

A laminate contains conductive circuit patterns, a substrate material, and an adhesive pattern or other bond. Each conductive circuit pattern and the substrate material are interconnected by the adhesive pattern or other bond, having its size and shape substantially matching the main outlines of each conductive circuit pattern. Each conductive circuit pattern has thin lines and thin interline spaces, patterned on top of the adhesive pattern or other bond by a removal of conductive material, such that the circuit pattern's thin interline spaces may have residues of the adhesive patterns or other bond. Outside the conductive circuit patterns' main outlines, the substrate material is substantially void of an adhesive or other bond, with the exception of edge areas of the main outlines.

A method and structure are provided for implementing stub-less printed circuit board (PCB) vias and custom interconnect through laser-excitation conductive track structures. Stub-less printed PCB vias are formed which terminate at desired signal layers by controlled laser excitation without stubs or the need to back-drill to remove such stubs.

A method for manufacturing traces of a printed circuit board (PCB) comprises an application of the periodic pulse reverse (PPR) pattern plating process. In the first stage, walls and bottoms in drilled holes of the PCB are modified with reduced graphene oxide (rGO) so that the vias can be formed by filling with copper and a very thin copper layer can be formed on the substrate through the electroplating process. In the second stage, a pattern of very fine traces with width/space less than 30/30 m is formed on the thin copper layer and then the traces are formed through the PPR pattern plating process. After removing unwanted copper layer, the traces with even thicknesses and square profiles are achieved and thus conform to requirements of the high density interconnection (HDI) technology.

A method for manufacturing traces of a printed circuit board (PCB) comprises an application of the periodic pulse reverse (PPR) pattern plating process. In the first stage, walls and bottoms in drilled holes of the PCB are modified with reduced graphene oxide (rGO) so that the vias can be formed by filling with copper and a very thin copper layer can be formed on the substrate through the electroplating process. In the second stage, a pattern of very fine traces with width/space less than 30/30 m is formed on the thin copper layer and then the traces are formed through the PPR pattern plating process. After removing unwanted copper layer, the traces with even thicknesses and square profiles are achieved and thus conform to requirements of the high density interconnection (HDI) technology.

A method for manufacturing a double-sided wiring circuit board includes a first step of preparing a laminate and a second step. The laminate includes a metal core layer, insulating layers, and conductor layers. The insulating layer has a region and an opening that are adjacent to each other. The insulating layer has a region including a part facing the region in a thickness direction, and an opening adjacent to the region. The conductor layer includes a wiring portion and a conductive portion. In the second step, the first and second etching treatments for etching the metal core layer through the openings are carried out to form a via portion having a periphery surrounded by a space, extending between the regions, and connected to the conductive portions.

A first through hole is formed in a base, a conductive layer covering an inner wall side surface of the first through hole is formed, a columnar electric conductor having a Vickers hardness of a value in a range of 30 Hv or more and 400 Hv or less is inserted into the first through hole formed with the conductive layer, pressure is applied in a vertical direction to the columnar electric conductor, and a second through hole is formed in the columnar electric conductor.

A first through hole is formed in a base, a conductive layer covering an inner wall side surface of the first through hole is formed, a columnar electric conductor having a Vickers hardness of a value in a range of 30 Hv or more and 400 Hv or less is inserted into the first through hole formed with the conductive layer, pressure is applied in a vertical direction to the columnar electric conductor, and a second through hole is formed in the columnar electric conductor.

Discussed generally herein are methods and devices for altering an effective series resistance (ESR) of a component. A device can include a substrate including electrical connection circuitry therein, a first via hole through a first surface of the substrate and contiguous with the electrical connection circuitry, a first conductive polymer with a resistance greater than a resistance of the electrical connection circuitry filling the first via hole, and a component electrically coupled to the first conductive polymer.

A multilayer wiring substrate that can realize a higher-density wiring structure is obtained. Provided is a multilayer wiring substrate, where a multilayer body including a first insulating layer and a second insulating layer stacked on the bottom surface of the first insulating layer includes printed wiring electrodes; the printed wiring electrodes are formed by printing with and sintering conductive paste; the printed wiring electrodes respectively include first wiring electrode portions located on the second insulating layer and second wiring electrode portions respectively joined to first wiring electrode portions; and the second wiring electrode portions respectively extend into through holes and, further, are exposed at the top surface of the first insulating layer.