A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

A through wiring substrate comprises a substrate having a pair of principal surfaces and a through hole penetrating between the pair of principal surfaces, the pair of principal surfaces and an inner surface of the through hole being electrically insulative; a through electrode provided on the inner surface of the through hole; a first wiring layer provided on one of the principal surfaces and connected to the through electrode; a second wiring layer provided on the other of the principal surfaces and connected to the through electrode; an underlying metal layer provided between the one of the principal surfaces and the first wiring layer; and catalyst metal particles existing between the underlying metal layer and the first wiring layer and between the through electrode and the inner surface of the through hole.

Horizontal methods of electroless metal plating with ionic catalysts have improved plating performance by reducing undesired foaming. The reduced foaming prevents loss of ionic catalyst from the catalyst bath and prevents scum formation which inhibits catalyst performance. The horizontal methods also inhibit ionic catalyst precipitation and improve adhesion of the ionic catalyst to the substrate. The horizontal method can be used to plate through-holes and vias of various types of substrates.

Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

A printed circuit board may include: a first circuit layer; a first insulating layer disposed on the first circuit layer; a high-rigidity layer disposed on the first insulating layer; and a second circuit layer disposed on the high-rigidity layer and connected to the first circuit layer by a first via extending through the first insulating layer and the high-rigidity layer, wherein a rigidity of the high-rigidity layer is greater than a rigidity of the first insulating layer.

Compositions and methods for silver plating onto metal surfaces such as PWBs in electronics manufacture to produce a silver plating which is greater than 80 atomic % silver, tarnish resistant, and has good solderability.

The invention eliminates defects generated in a metal filling a through hole of a printed board by changing an angle at which a plating solution is sprayed or by changing a posture of the printed board at a time point in a process of precipitating the metal from the plating solution and filling the through hole with the precipitated metal while the plating solution or air bubbles are being sprayed onto the printed board.

A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.

A PCB having multiple stacked layers laminated together. The laminated stack includes regular flow prepreg and includes an embedded cavity, the perimeter of which is formed by a photo definable, or photo imageable, polymer structure, such as a solder mask dam. The solder mask dam defines cavity dimensions and prevents prepreg resin flow into the cavity during lamination.

A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the inner core layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.