Methods for producing a printed circuit board and printed circuit boards are disclosed, including a method in which a slot is formed in a substrate, the substrate having at least three layers with the slot extending through at least two of the layers. The slot has a length and a width with the length being greater than the width. The sidewall of the substrate surrounding the slot is coated with a conductive layer. The conductive layer is separated into at least two segments that are electrically isolated along the side wall of the substrate.

The invention relates to: a photosensitive resin composition containing: (A) a photopolymerizable compound having an ethylenically unsaturated group and an acidic substituent, (B) an epoxy resin, and (C) an active ester compound, and a method for producing it, a photosensitive resin film using the photosensitive resin composition, a multilayer printed wiring board and a method for producing it, and a semiconductor package.

A wiring substrate includes: a base material; a first through-hole and a second through-hole that are formed in the base material; magnetic material that is filled in the first through-hole; a third through-hole that is formed in the magnetic material; a first plating film that covers an inner wall surface of the third through-hole; and a second plating film that covers an inner wall surface of the second through-hole and the first plating film. The first plating film includes a first electroless plating film that is in contact with the inner wall surface of the third through-hole, and a first electrolytic plating film that is laminated on the first electroless plating film.

A wiring substrate includes a first insulating layer, a first conductor layer, a second insulating layer, a second conductor layer, a connection conductor penetrating through the second insulating layer and connecting the first and second conductor layers, and a coating film formed on a surface of the first conductor layer such that the coating film is adhering the first conductor layer and the second insulating layer. The first conductor layer includes a conductor pad and a wiring pattern such that the conductor pad is in contact with the connection conductor and the wiring pattern is covered by the coating film, the conductor pad of the first conductor layer has a surface facing the second insulating layer and having a first surface roughness higher than a surface roughness of a surface of the wiring pattern, and the coating film has opening such that the opening is exposing the conductor pad entirely.

A method for manufacturing a printed circuit board includes forming a through hole in an insulating layer of the printed circuit board, filling the through hole by plating to form a plating layer on the insulating layer, and removing the plating layer from the insulating layer; and forming a circuit pattern on the insulating layer.

Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.

A component carrier with a stack including an electrically insulating layer structure and an electrically insulating structure has a tapering blind hole formed in the stack and an electrically conductive plating layer extending along at least part of a horizontal surface of the stack outside of the blind hole and along at least part of a surface of the blind hole. A minimum thickness of the plating layer at a bottom of the blind hole is at least 8 μm. A demarcation surface of the plating layer in the blind hole and facing away from the stack extends laterally outwardly from the bottom of the blind hole towards a lateral indentation and extends laterally inwardly from the indentation up to an outer end of the blind hole. An electrically conductive structure fills at least part of a volume between the plating layer and an exterior of the blind hole.

Structures that implement three-dimensional (3D) conductive material (e.g., copper) in printed circuit boards (PCBs) are disclosed. 3D (three-dimensional) conductive material may include trenches and/or buried vias that are filled with conductive material in the PCBs. Trenches may be formed in build-up layers of a PCB by overlapping multiple laser drilled vias. The trenches may be filled with conductive material using electroplating process(es). Buried vias may be formed through the core layers of the PCB by mechanical drilling. The buried via may be filled with solid conductive material using a combination of electroless plating and electrolytic plating of conductive material. Various PCB structures are disclosed that implement combinations of these trenches and/or these buried vias filled with conductive material.

A conductive network fabrication process is provided and includes filling a hole formed in a substrate with dielectric material, laminating films of the dielectric material on either side of the substrate, opening a through-hole through the dielectric material at the hole, depositing a conformal coating of dielectric material onto an interior surface of the through-hole and executing seed layer metallization onto the conformal coating in the through-hole to form a seed layer extending continuously along an entire length of the through-hole.