A method of forming a multi-layer circuit on a curved substrate includes forming, by a laser direct structuring process, a first layer of the multi-layer circuit on a first surface of the curved substrate. The method includes applying a first layer of paint to the first layer of the multi-layer circuit. The method includes forming, by the laser direct structuring process, a second layer of the multi-layer circuit on the first layer of the paint and electrically coupled to the first layer of the multi-layer circuit. The method includes applying a second layer of paint over the second layer of the multi-layer circuit and forming, by the laser direct structuring process, a third layer of the multi-layer circuit on the second layer of the paint and electrically coupled to the second layer of the multi-layer circuit.

A plating apparatus including a plating bath, a substrate holder to be arranged in the plating bath and adapted to hold a substrate, an anode for generating an electric field between the substrate and the anode, and at least one electric field shielding body for shielding the substrate holder and a part or the whole of the electric field, wherein the electric field shielding body has an opening portion for allowing the electric field between the substrate and the anode to pass therethrough, and is configured so as to be capable of adjusting an opening size in a first direction of the opening portion and an opening size in a second direction of the opening portion independently of each other.

An interconnect structure includes a first conductor, a second conductor, a dielectric block, a substrate, and a pair of conductive lines. The first conductor and the second conductor form a differential pair design. The dielectric block surrounds the first conductor and the second conductor. The first conductor is separated from the second conductor by the dielectric block. The substrate surrounds the dielectric block and is spaced apart from the first conductor and the second conductor. The pair of conductive lines is connected to the first conductor and the second conductor, respectively, and extends along a top surface of the dielectric block and a top surface of the substrate.

A multi-layer circuit board, successively constituted by surface sticking layer, single-layer circuit board, middle sticking layer, single-layer circuit board, surface sticking layer, said multi-layer circuit board is provided with a hole, a hole wall of said hole is formed with conductive seed layer, and partial outer surface of said surface sticking layer is formed with a circuit pattern layer of conductive seed layer, wherein said conductive seed layer comprises a ion implantation layer implanting below the hole wall of said hole and below partial outer surface of said surface sticking layer.

A printed circuit board includes an insulating layer; a metal pad disposed on one side of the insulating layer; a via hole penetrating through the insulating layer to expose at least a portion of the metal pad; and a via filling at least a portion of the via hole, wherein the via comprises a first metal layer and a second metal layer disposed on the first metal layer, and an average size of grains in the first metal layer and an average size of grains in the second metal layer are different from each other.

A method of fabricating a substrate having a through via includes: providing a carrier board having a release layer thereon; attaching the substrate onto the carrier board via the release layer; applying a light beam to the substrate to form a first blind hole in the substrate, wherein the first blind hole penetrates a first surface and a second surface of the substrate; performing an enlargement process on the first blind hole to form a second blind hole; forming a through via in the second blind hole; and performing a de-bonding process to release the substrate having a through via from the carrier board.

A method for optimized filling holes and manufacturing fine lines on a printed circuit board (PCB) carries out the two processes separately. The inner wall of the hole is metalized with reduced graphene oxide (rGO) and then electroplated to fill the hole with copper. The processes are individually performed and thus operating parameters are considered independently. As a result, the copper-plating fillings are evenly compact and the fine lines have square profiles.

A wiring substrate includes a first insulating layer, a first conductor layer formed on the first insulating layer, a second insulating layer formed on the first conductor layer, a second conductor layer formed on the second insulating layer, and a via conductor formed in the second insulating layer such that the via conductor is connecting the first and second conductor layers. The second insulating layer has a via hole in which the via conductor is formed, and the via conductor includes a first plating film and a second plating film such that the first plating film has a bottom portion formed at bottom of the via hole and a side portion formed on side of the via hole and separated from the bottom portion by gap and that the second plating film is covering the gap of the first plating film and at least part of the first plating film.

A circuit board has a dielectric core, a foil top surface, and a thin foil bottom surface with a foil backing of sufficient thickness to absorb heat from a laser drilling operation to prevent the penetration of the thin foil bottom surface during laser drilling. A sequence of steps including a laser drilling step, removing the foil backing step, electroless plating step, patterned resist step, electroplating step, resist strip step, tin plate step, and copper etch step are performed, which provide dot vias of fine linewidth and resolution.

Provided is a display device and an electronic apparatus that prevent the occurrence of failure in the connection between a mounting substrate and an electronic component. The display device includes an interconnection layer provided on a support substrate, a plurality of insulating layers provided above the interconnection layer, an opening provided in parts of the insulating layers, and a metal layer electrically connected to the interconnection layer and filling the opening up to a height below a layer surface of the insulating layer.