A component carrier includes a stack having a first electrically insulating layer structure and a first electrically conductive layer structure arranged on the first electrically insulating layer structure. The first electrically insulating layer structure has at least one first covered portion, which is covered by the first electrically conductive layer structure, and at least one first non-covered portion, which is not covered by the first electrically conductive layer structure. The first electrically insulating layer structure defines a recess at the at least one first non-covered portion.

A substrate structure with high reflectance includes a base material, a patterned circuit layer, an insulating layer and a metal reflecting layer. The base material includes a first surface and a second surface opposite to the first surface. The patterned circuit layer is disposed on the first surface. The insulating layer covers the patterned circuit layer and a part of the first surface exposed by the patterned circuit layer. The metal reflecting layer covers the insulating layer, and a reflectance of the metal reflecting layer is substantially greater than or equal to 85%. A manufacturing method of a substrate structure with high reflectance is also provided.

A substrate structure with high reflectance includes a base material, a patterned circuit layer, an insulating layer and a metal reflecting layer. The base material includes a first surface and a second surface opposite to the first surface. The patterned circuit layer is disposed on the first surface. The insulating layer covers the patterned circuit layer and a part of the first surface exposed by the patterned circuit layer. The metal reflecting layer covers the insulating layer, and a reflectance of the metal reflecting layer is substantially greater than or equal to 85%. A manufacturing method of a substrate structure with high reflectance is also provided.

A package carrier includes a substrate, at least one interposer disposed in at least one opening of the substrate, a conductive structure layer, a first build-up structure, and a second build-up structure. The interposer includes a glass substrate, at least one conductive via, at least one first pad, and at least one second pad. The conductive via passes through the glass substrate, and the first and the second pads are disposed respectively on an upper surface and a lower surface of the glass substrate opposite to each other and are connected to opposite ends of the conductive via. The conductive structure layer is disposed on the substrate and is structurally and electrically connected to the first and the second pads. The first and the second build-up structures are disposed respectively on the first and the second surfaces of the substrate and are electrically connected to the conductive structure layer.

A base material is provided. A first patterned circuit layer and a second patterned circuit layer are formed on a first surface and a second surface of the base material. A first insulation layer and a metal reflection layer are provided on the first patterned circuit layer and a portion of the first surface exposed by the first patterned circuit layer, wherein the metal reflection layer covers the first insulation layer, and a reflectance of the metal reflection layer is substantially greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer. A first ink layer is formed on the first insulation layer before the metal reflection layer is formed.

Methods and structures corresponding to superconducting apparatus including superconducting layers and traces are provided. A method for forming a superconducting apparatus includes forming a first dielectric layer on a substrate by depositing a first dielectric material on the substrate and curing the first dielectric material at a first temperature. The method further includes forming a first superconducting layer comprising a first set of patterned superconducting traces on the first dielectric layer. The method further includes forming a second dielectric layer on the first superconducting layer by depositing a second dielectric material on the first superconducting layer and curing the second dielectric material at a second temperature, where the second temperature is lower than the first temperature. The method further includes forming a second superconducting layer comprising a second set of patterned superconducting traces on the second dielectric layer.

The method of dicing a wiring substrate that includes a core substrate having a front surface and a rear surface at least one of which is provided with an adhesive layer and a rim pattern thereon. The adhesive layer is provided with a laminate that has wiring layers and insulating layers, laminating. The rim pattern is provided with the insulating layers laminated thereon. The method includes steps of forming separation grooves by removing portions of the insulating layers laminated on the rim pattern to expose the rim pattern; exposing at least one of the front and rear surfaces of the core substrate by dissolving and removing the rim pattern of the groove bottoms; and dicing the core substrate exposed at groove bottoms, along cutting margins each being smaller than a groove width of each of the groove bottoms.

A printed wiring board includes an insulating substrate, a first conductor layer formed on a first surface of the substrate, a second conductor layer formed on a second surface of the substrate, and through-hole conductors formed through the substrate and connecting the first and second conductor layers. The substrate has openings formed such that each opening extends from the first to second surfaces of the substrate, and magnetic material filling the openings and forming through holes such that each through hole extends from the first to second surfaces of the substrate, the through-hole conductors are formed on sidewalls of the through holes in the magnetic material, and the magnetic material includes resin and particles including magnetic metal such that the particles include a group of particles forming the sidewalls of the through holes and that each particle in the group has a substitution plating film formed on a surface thereof.

A circuit board includes a glass substrate having a first surface and a second surface facing away from the first surface; a first coil wiring pattern formed on the first surface and a second coil wiring pattern formed on the second surface, the first and second coil wiring patterns constituting part of a coil; a through hole extending through a predetermined portion of the glass substrate from an end of the first coil wiring pattern to an end of the second coil wiring pattern; a through hole inner conductive surface formed on the inner side of the through hole, the first and second coil wiring patterns and the through hole inner conductive surface constituting the coil wound around a direction perpendicular to an axis of the through hole and to a direction in which the first and second coil wiring patterns extend.

The present technology relates to a semiconductor device and a manufacturing method, an imaging device, and an electronic apparatus that enable component mounting with high flatness at low cost. A semiconductor device includes: a core substrate: a multilayer wiring layer that includes a plurality of conductive layers and a plurality of insulating layers, and is formed on a surface of the core substrate; an opening that is formed in the multilayer wiring layer, and penetrates through at least the outermost insulating layer farthest from the core substrate among the plurality of insulating layers; and a mount element connected to a pad portion provided on a predetermined conductive layer located closer to the core substrate than the outermost conductive layer farthest from the core substrate among the plurality of conductive layers in the opening. The present technology can be applied to imaging devices.