An apparatus is provided which comprises: a plurality of organic dielectric layers forming a substrate, a plurality of first conductive contacts on a top surface of the substrate, a plurality of second conductive contacts on a bottom surface of the substrate, a plurality of third conductive contacts on a side wall surface of the substrate, and one or more discrete capacitor(s) coupled with the third conductive contacts on the side wall surface. Other embodiments are also disclosed and claimed.

A method of preparing a graphene circuit pattern, a substrate and an electronic product are disclosed. The method of preparing a graphene circuit pattern includes: immersing a metal circuit pattern in a graphene oxide solution to cause a redox reaction between the metal circuit pattern and graphite oxide, thereby forming the graphene circuit pattern. The graphene circuit pattern may be directly formed at a location of the metal circuit pattern, and is simple in production process, low in cost, and suitable for mass production.

A semiconductor device includes: a thick copper member in which a semiconductor chip is mounted; a printed circuit board that is disposed on a front surface of the thick copper member and provided with an opening exposing a part of the front surface of the thick copper member, a wiring pattern, and conductive vias connecting the pattern and the thick copper member; a semiconductor chip mounted on the front surface of the thick copper member exposed through the opening and connected to the pattern by a metal wire; an electronic component mounted on a front surface of the printed circuit board opposite to a side facing the thick copper member and connected to the pattern; and a cap or an epoxy resin sealing the front surface of the printed circuit board opposite to a side facing the thick copper member, the chip, the component, and the metal wire.

An insulated metal substrate (IMS) includes a metal substrate, an insulating layer, a plastic frame, and a plurality of conductive metal pads. The insulating layer is located on the metal substrate. The plastic frame is located on the insulating layer and has a plurality of aperture areas. The conductive metal pads are located on the insulating layer and are respectively located in the aperture areas, and the conductive metal pads have sidewalls are in contact with the plastic frame.

Provided is a circuit board including: a metal core layer having a first main surface capable of supporting a mounting component and a second main surface which is opposite to the first main surface; a first exterior coating base material which is arranged facing the first main surface; and a second exterior coating base material which is arranged facing the second main surface and includes a heat dissipation layer having a via which is connected to the second main surface.

The present disclosure provides a composite conductive substrate exhibiting enhanced properties both in the folding endurance and the electric conductivity and a method of manufacturing the composite conductive substrate. A composite conductive substrate according to an exemplary embodiment of the present disclosure includes: an insulating layer; a metal nanowire structure embedded beneath one surface of the insulating layer; and a metal thin film coupled to the metal nanowire structure. The composite conductive substrate may be fabricated in an order of the insulating film, the metal nanowire structure, and the metal thin film, or vice versa.

A carrier board and a power module using the same are disclosed. The carrier board includes a main body, two metal-wiring layers and at least one metal block. The main body includes at least two terminals and a surface. The two terminals are disposed on the surface. The two metal-wiring layers are disposed on the main body to form two parts of metal traces connected to the two terminals, respectively. The at least one metal block is embedded in the main body and connected to one of the two terminals. A thickness of the two parts of metal traces is less than that of the metal block. The two terminals connected by the two parts of metal traces have a loop inductance less than or equal to 1.4 nH calculated at a frequency greater than 1 MHz.

An electroplating method of a circuit board includes: providing a multi-layer board having a conductive layer embedded therein; penetratingly forming a thru-hole and at least one penetrating hole in the multi-layer board, and forming a conductive portion on an inner wall defining the thru-hole and connected to the conductive layer, wherein the at least one penetrating hole is located at one side of the thru-hole, and an annular portion of the conductive layer exposed from the at least one penetrating hole is defined as an electroplated region; and electroplating the electroplated region to be formed with a metal post by applying a current to the conductive portion, wherein the metal post is filled in the at least one penetrating hole and is connected to the electroplated region.

An electro-optical structure including at least one optical component and a plurality of electric components arranged on a common printed circuit board is disclosed herein. The printed circuit board includes a plate-shaped base body made of molybdenum or an Invar material. An optical bench including a printed circuit board with a plate-shaped base body of molybdenum or an Invar material is also disclosed herein.

Circuit board includes conductive plate, core dielectric layer, metallization layer, first build-up stack, second build-up stack. Conductive plate has channels extending from top surface to bottom surface. Core dielectric layer extends on covering top surface and side surfaces of conductive plate. Metallization layer extends on core dielectric layer and within channels of conductive plate. Core dielectric layer insulates metallization layer from conductive plate. First build-up stack is disposed on top surface of conductive plate and includes conductive layers alternately stacked with dielectric layers. Conductive layers electrically connect to metallization layer. Second build-up stack is disposed on bottom surface of conductive plate. Second build-up stack includes bottommost dielectric layer and bottommost conductive layer. Bottommost dielectric layer covers bottom surface of conductive plate. Bottommost conductive layer is disposed on bottommost dielectric layer and electrically connects to metallization layer. First build-up stack includes more conductive and dielectric layers than second build-up stack.