The power switching module includes first and second subassemblies that are superimposed on top of each other to form a stack and that comprise first and second electronic power switches forming a bridging arm, respectively. The module comprises a metal central sheet (LW7) and first and second metal end sheets (LW2, LW12) forming top and bottom ends of the stack. According to the invention, the module also comprises first, second and third metal terminal rods (1, 2, 3) that extend through the stack and open onto at least one of the top and bottom ends thereof, the first, second and third rods being in electrical continuity with the first and second metal end sheets and the metal central sheet, respectively.

An insulated metal substrate (IMS) includes a metal substrate, an insulating layer, a plastic frame, and a plurality of conductive metal pads. The insulating layer is located on the metal substrate. The plastic frame is located on the insulating layer and has a plurality of aperture areas. The conductive metal pads are located on the insulating layer and are respectively located in the aperture areas, and the conductive metal pads have sidewalls are in contact with the plastic frame.

The present disclosure provides a power module, a chip-embedded package module and a manufacturing method of the chip-embedded package module. The chip-embedded package module includes: a chip having a first surface and a second surface that are disposed oppositely; a first plastic member including a first cover portion and a first protrusion; and a second plastic member including a second cover portion and a second protrusion. A height difference discontinuous interface structure is formed between the top surface of the second protrusion and the second surface of the chip, which cuts off a passage for expansion of delamination at an edge position of the chip, thereby effectively suppressing generation of the delamination.

A circuit board includes a core layer including a plurality of metal layers laminated one over another, a bottommost metal layer of the plurality of metal layers being thickest, and a topmost metal layer of the plurality of metal layer being thinnest; an upper insulating layer and an upper conductive pattern provided over a top surface of the core layer; and a lower insulating layer and a lower conductive pattern provided below a bottom surface of the core layer, wherein the topmost metal layer of the core metal layer is patterned to have a prescribed shaped section that serves as wiring and that is connected to the upper conductive pattern, wherein a metal ratio that is defined as a ratio of an area that is formed of metal relative to an entire area in a plan view is higher in the bottommost metal layer than in the topmost metal layer.

A method for forming a multilayered circuit pattern on a surface of a 3D metal board includes: forming a first insulation layer on the surface of the 3D metal board; forming a first conductive pattern on the first insulation layer; forming a second insulation layer on the first conductive pattern except for a predetermined region; forming a second conductive pattern on the second insulation layer; and forming a third insulation layer on the second conductive pattern except for one or more circuit element mounting regions.

An electroplating method of a circuit board includes: providing a multi-layer board having a conductive layer embedded therein; penetratingly forming a thru-hole and at least one penetrating hole in the multi-layer board, and forming a conductive portion on an inner wall defining the thru-hole and connected to the conductive layer, wherein the at least one penetrating hole is located at one side of the thru-hole, and an annular portion of the conductive layer exposed from the at least one penetrating hole is defined as an electroplated region; and electroplating the electroplated region to be formed with a metal post by applying a current to the conductive portion, wherein the metal post is filled in the at least one penetrating hole and is connected to the electroplated region.

A method of manufacturing a component carrier is disclosed. The method includes forming a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; patterning a front side of the stack using a first photo-imageable dielectric; and patterning a back side of the stack. A component carrier is also disclosed.

A printed wiring board includes a core substrate having cavity to accommodate an electronic component and including a front conductor layer formed on front side of the core substrate, and a back conductor layer formed on back side of the core substrate, through-hole conductors formed through the core substrate such that the through-hole conductors connect the front and back conductor layers of the core substrate, a front build-up layer formed on front surface of the core substrate and including interlayer insulating layers and conductor layers, and a back build-up layer formed on back surface of the core substrate and including interlayer insulating layers and conductor layers. The conductor layers in the front build-up layer include a conductor layer sandwiching one of the interlayer insulating layers with the front conductor layer such that the conductor layer and the front conductor layer have the same electric potential in region surrounding the cavity.

A circuit board structure includes a first core layer, a first build-up layer and a second build-up layer. The first core layer has a first surface and a second surface opposite to the first surface, wherein the first core layer includes a core dielectric material layer and at least one patterned conductive plate embedded within the core dielectric material layer, the core dielectric material layer includes a first sub-dielectric material and a second sub-dielectric material, and at least one interface exists in between the first sub-dielectric material and the second sub-dielectric material. The first build-up layer is disposed on the first surface of the first core layer, and the second build-up layer is disposed on the second surface of the first core layer.

A semiconductor module includes a metal core layer that includes: a first metal layer and a second metal layer on the first metal layer, wherein a portion of the second metal layer is removed to expose a surface of the first metal layer, the removed portion of the second metal layer defining a cavity in the metal core layer having the exposed surface of the first metal layer as a bottom surface, and at least one of a side wall and the bottom surface of the cavity has a smoother surface profile than a surface of the first metal layer that is not exposed by the cavity and under the second metal layer; and a semiconductor element provided in the cavity, affixed to the bottom surface of the cavity with a fixing material containing a resin component.