A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the inner core layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.

Embodiments of present invention provide a multilayer printed circuit board. The printed circuit board includes a first conducting layer (CL) having a first measurement mark area (MMA) and a second CL having a second MMA. A first polygonal measurement mark (MM) in the first MMA and a second and a third polygonal MM in the second MMA, wherein the second polygonal MM is positioned along an extended first angle bisector bisecting a first vertex of the first polygonal MM and a first vertex of the second polygonal MM is substantially aligned with the first vertex of the first polygonal MM, and wherein the third polygonal MM is positioned along an extended second angle bisector bisecting a second vertex of the first polygonal MM and a first vertex of the third polygonal MM is substantially aligned with the second vertex of the first polygonal MM.

Electronic modules having complex contact structures may be formed by encapsulating panels containing pluralities of electronic modules delineated by cut lines and having conductive interconnects buried within the panel along the cut lines. Holes defining contact regions along the electronic module sidewall may be cut into the panel along the cut lines to expose the buried interconnects. The panel may be metallized, e.g. by a series or processes including plating, on selected surfaces including in the holes to form the contacts and other metal structures followed by cutting the panel along the cut lines to singulate the individual electronic models. The contacts may be located in a conductive grove providing a castellated module.

The present invention relates to an improved system and method for manufacturing flexible circuit boards (FSBs) using optical alignment and various bonding systems. The invention provides an improved process to connect together the layers of rigid-flex, flexible, and printed circuit boards while maintaining alignment of the layers prior to and possibly after a lamination step. An optical alignment system is provided, a preferred arrangement is enabled as an automated pinless bonding system (PBS), for securely gripping, aligning, transferring, and clamping, bonding and moving a bonded FSB employing a multi-axis orientation. An alternative manual optical alignment and bonding system is provided.

According to one embodiment, a misalignment measuring apparatus includes: an input circuit; a storage medium; a first circuit configured to, in a first calibration pattern, calculate a second misalignment amount; a second circuit configured to, using a first image of a second calibration pattern, calculate a third misalignment amount; a third circuit configured to calculate a coefficient indicating; and a fourth circuit configured to, using a second image corresponding to the first and second patterns, calculate a third center position of a third contour and calculate the first misalignment amount between the first pattern and the second pattern based on the fourth misalignment amount and the coefficient.

A method of compensating misalignment during manufacturing laminate-type component carriers is disclosed. The method includes detecting an image of a region of interest of a component carrier structure during manufacturing the component carriers based on the component carrier structure, identifying a structural feature in the image of the region of interest showing misalignment with respect to a target design, and at least partially compensating the identified misalignment of the structural feature by modifying the target design of at least one correlated structural feature to be manufactured subsequently, wherein the at least one correlated structural feature is correlated to said structural feature showing misalignment.

According to one embodiment, a misalignment measuring apparatus includes: an input circuit; a storage medium; a first circuit configured to, in a first calibration pattern, calculate a second misalignment amount; a second circuit configured to, using a first image of a second calibration pattern, calculate a third misalignment amount; a third circuit configured to calculate a coefficient indicating; and a fourth circuit configured to, using a second image corresponding to the first and second patterns, calculate a third center position of a third contour and calculate the first misalignment amount between the first pattern and the second pattern based on the fourth misalignment amount and the coefficient.

A phased-array, conformal antenna and a method for forming same are disclosed. The method comprises forming a substantially planar layered antenna structure by fabricating a printed circuit board (PCB) on a substantially planar first substrate, adhering the PCB to a second substantially planar substrate, the second substantially planar substrate comprising an aerogel, adhering a plurality of antenna elements to the substantially planar second substrate to form the phased-array, adhering a protective layer to the one or more antenna elements, and shaping the substantially planar layered antenna structure to form a substantially curved layered antenna structure.

The invention, which relates to the technical field of inductance embedding, specifically discloses an embedded circuit board. The embedded circuit board includes: at least layer of sub-body, where preset positions of the sub-bodies are provided with through slots; and an inductance element embedded within the slots and configured to be spaced apart from sidewalls of the slots. In the above manner, it is possible to make the embedded circuit board of the present application structurally compact, highly integrated, widely applicable, and safe and reliable.

A method of planning the manufacture of component carriers includes defining a set of final product parameters as a target for component carriers to be manufactured, ranking the process parameters concerning their impact on the final product parameters, selecting a subset of higher ranked process parameters, inputting the selected subset of process parameters for processing by an artificial intelligence module, and determining an action plan for the manufacturing based on an output of the artificial intelligence module, where the product parameters are influenceable by a set of process parameters settable during the manufacturing method.