A method for manufacturing a double-sided wiring circuit board includes a first step of preparing a laminate and a second step. The laminate includes a metal core layer, insulating layers, and conductor layers. The insulating layer has a region and an opening that are adjacent to each other. The insulating layer has a region including a part facing the region in a thickness direction, and an opening adjacent to the region. The conductor layer includes a wiring portion and a conductive portion. In the second step, the first and second etching treatments for etching the metal core layer through the openings are carried out to form a via portion having a periphery surrounded by a space, extending between the regions, and connected to the conductive portions.

A method of fabricating a packaging substrate includes following steps: providing a carrier board having two opposite surfaces, forming on each of the surfaces a plurality of first metal bumps; covering the carrier board and the first metal bumps with a first dielectric layer that has a plurality of first intaglios which exposes a top surface and side surface of the first metal bumps; forming a conductive seedlayer on the first dielectric layer and the first metal bumps; forming a metal layer on the conductive seedlayer; removing a portion of the metal layer and the conductive seedlayer that is higher than the top surface of the first dielectric layer, and forming a first circuit layer in the first intaglios; forming a built-up structure on the first circuit layer and the first dielectric layer, forming a pair of upper and lower entire packaging substrates.

A manufacturing method of a package substrate includes forming a patterned first dielectric layer on a carrier; forming a first wiring layer on a first surface of the first dielectric layer facing away from the carrier, a wall surface facing one of the openings of the first dielectric layer, and the carrier in one of the openings; forming a first conductive pillar layer on the first wiring layer on the first surface; forming a second dielectric layer on the first surface, the first wiring layer, and the openings, wherein the first conductive pillar layer is exposed from the second dielectric layer; forming a second wiring layer on the exposed first conductive pillar layer and the second dielectric layer; forming an electrical pad layer on the second wiring layer; and forming a third dielectric layer on the second dielectric layer and the second wiring layer.

The problem of the present invention is to provide a method for forming a wiring laminated structure which enables forming a post electrode to protrude with a predetermined height on a lower electrode and to enable preventing interlayer connection failures or short defects, and the problem is solved by a method for forming a wiring laminated structure including impacting a droplet of a conductive ink discharged from a nozzle 11 of an inkjet head 10 onto a lower electrode 2 provided on a base material to form a post electrode with the use of the conductive ink, the conductive ink being a liquid repellent conductive ink which develops liquid repellency in the post electrode, and the post electrode being formed to protrude with a predetermined height on the lower electrode 2 by discharging the droplet under conditions that the droplet is not divided or the number of divided drop becomes one or less before the droplet impacts on the lower electrode 2.

This disclosure provides a package substrate which includes: a first conductive layer having a first conductive area and a second conductive area; a package unit layer disposed on the first conductive layer and including a first circuit device having a first terminal connected to the first conductive area and a second terminal connected to the second conductive area, a first conductive pillar connected to the first conductive area, and an encapsulant material; and a second conductive layer disposed on the package unit layer and having a first metal wire connected to the first conductive pillar.

A printed wiring board includes a conductor layer including a conductor circuit, a resin insulating layer formed on the conductor layer and having a via opening reaching to the conductor circuit of the conductor layer, and a via conductor formed in the via opening of the resin insulating layer such that the via conductor is connecting to the conductor circuit of the conductor layer. The conductor circuit of the conductor layer has a first conductor portion and a second conductor portion integrally formed such that the first conductor portion is connected to the via opening of the resin insulating layer, that the second conductor portion is surrounding the first conductor portion and that the first conductor portion has a thickness which is greater than a thickness of the second conductor portion.

An integrated circuit package and manufacturing method thereof are described. The integrated circuit package includes pin up conductive plating to form an interconnect, where an opening on a patterned fifth layer photo-resist material located at bottom portion of a base developed for etching selectively the base to form at least an internal opening and at least a positioning opening, wherein the internal opening corresponds with an inside area of a first patterned conductive layer, and the positioning opening corresponds with an outside area of the first patterned conductive layer.

Provided is a landless multilayer circuit board and a manufacturing method thereof. The manufacturing method includes steps of forming a first circuit on a first substrate, patterning a photoresist layer to form at least one via between the first circuit and a second circuit, forming at least one connecting pillar in the at least one via, removing the photoresist layer, forming a second substrate to cover the at least one connect pillar, and forming the second circuit on the second substrate. The second circuit is connected to the first circuit through the at least one connecting pillar. When the second circuit is formed, the at least one via does not need to be filled, thereby making the second circuit flat.

This disclosure relates generally to an electronic chip package that can include a die and a buildup layer substantially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the buildup layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic chip package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic chip package different from the first major surface.

An interconnect element 130 can include a dielectric layer 116 having a top face 116b and a bottom face 116a remote from the top face, a first metal layer defining a plane extending along the bottom face and a second metal layer extending along the top face. One of the first or second metal layers, or both, can include a plurality of conductive traces 132, 134. A plurality of conductive protrusions 112 can extend upwardly from the plane defined by the first metal layer 102 through the dielectric layer 116. The conductive protrusions 112 can have top surfaces 126 at a first height 115 above the first metal layer 132 which may be more than 50% of a height of the dielectric layer. A plurality of conductive vias 128 can extend from the top surfaces 126 of the protrusions 112 to connect the protrusions 112 with the second metal layer.