A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.

A printed wiring board includes a conductor layer including a conductor circuit, a resin insulating layer formed on the conductor layer and having a via opening reaching to the conductor circuit of the conductor layer, and a via conductor formed in the via opening of the resin insulating layer such that the via conductor is connecting to the conductor circuit of the conductor layer. The conductor circuit of the conductor layer has a first conductor portion and a second conductor portion integrally formed such that the first conductor portion is connected to the via opening of the resin insulating layer, that the second conductor portion is surrounding the first conductor portion and that the first conductor portion has a thickness which is greater than a thickness of the second conductor portion.

This disclosure provides a package substrate which includes: a first conductive layer having a first conductive area and a second conductive area; a package unit layer disposed on the first conductive layer and including a first circuit device having a first terminal connected to the first conductive area and a second terminal connected to the second conductive area, a first conductive pillar connected to the first conductive area, and an encapsulant material; and a second conductive layer disposed on the package unit layer and having a first metal wire connected to the first conductive pillar.

A substrate structure and a manufacturing method thereof are provided. The substrate structure comprises a metal carrier, a dielectric material layer, a first conductive wiring layer, a second conductive wiring layer and a conductive pillar layer. The first conductive wiring layer is disposed on a surface of the metal carrier. The dielectric material layer is disposed on a surface of the first conductive wiring layer. The conductive pillar layer is disposed inside the dielectric material layer, and located between the first conductive wiring layer and the second conductive wiring layer. The conductive pillar layer has at least one conductive pillar. The conductive pillar is electrically connected to the first conductive wiring layer and the second conductive wiring layer.

A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.

A printed wiring board includes a resin insulating layer, a projecting conductor layer formed on a surface of the resin insulating layer such that the projecting conductor layer is projecting from the surface of the resin insulating layer, and an integral conductor structure formed in the resin insulating layer and including a via conductor portion and an embedded conductor layer portion such that the embedded conductor layer portion is embedded in the resin insulating layer on the opposite side of the resin insulating layer with respect to the projecting conductor layer and has an exposed surface exposed from the resin insulating layer and the via conductor portion is formed through the resin insulating layer and is connecting the embedded conductor layer portion and projecting conductor layer. The projecting conductor layer and integral conductor structure are formed such that the projecting conductor layer and integral conductor structure are individual conductor structures.

A printed wiring board includes a lowermost resin insulating layer, a first conductor layer formed on a first surface of the lowermost resin insulating layer, a conductor post formed in the lowermost resin insulating layer such that the conductor post has an upper surface facing the first surface and a lower surface on the opposite side with respect to the upper surface, a semiconductor element embedded in the lowermost resin insulating layer such that the semiconductor element has an electrode facing the first surface and is positioned on a second surface side of the lowermost resin insulating layer, and via conductors formed in the lowermost resin insulating layer and including a first via conductor and a second via conductor such that the first via conductor is connecting the first conductor layer and the conductor post and that the second via conductor is connecting the first conductor layer and the electrode.

[Object] Provided is a printed circuit board ensuring a degree of freedom in circuit design and unlikely to cause a circuit connection failure. [Solving Means] A middle interlayer circuit 11, an upper surface side interlayer circuit 12, and a lower surface side interlayer circuit 13 are formed from a connection surface-less integral conductor. In addition, a connection surface 33 between the upper surface side interlayer circuit 12 and an upper surface side surface layer circuit 14 and a connection surface 34 between the lower surface side interlayer circuit 13 and a lower surface side surface layer circuit 15 lack a connection surface in a plate thickness direction, and thus a satisfactory connection state is achieved. Accordingly, a first circuit 10 is unlikely to cause a connection failure. In addition, the upper surface side interlayer circuit 12 and the lower surface side interlayer circuit 13 can be disposed at misaligned positions in the plane direction of the printed circuit board, and thus the degree of freedom in circuit design increases. Plane circuits 24 and 16 not connected to the first circuit can be disposed with insulating layers 31 and 32 sandwiched below the upper surface side interlayer circuit 12 or above the lower surface side interlayer circuit 13.

The present disclosure provides a printed circuit board and a method thereof. The printed circuit board has a first substrate, at least one first trace layer and at least one second trace layer. The first substrate has a first surface and a second surface. The first surface and the second surface are corresponding to each other along an axis. The first trace layer is formed on the first surface and/or the second surface of the first substrate. The first trace layer has at least one first trace and at least one first gap beside the first trace by etching. The second trace layer is formed on the first trace layer. The second trace layer has at least one second trace and at least one second gap beside the second trace by etching.

A ceramic wiring board that includes a ceramic insulator and a via-conductor. The ceramic insulator includes a crystalline constituent and an amorphous constituent. The via-conductor includes a metal and an oxide. The crystalline constituent and the oxide include at least one metal element in common. A tubular region having a thickness of 5 m adjoins and surrounds the via-conductor and has a higher concentration of the metal element than the ceramic insulator.